Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-08-05
2001-06-26
Robertson, David L. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S120000, C700S028000
Reexamination Certificate
active
06253286
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an apparatus for data processing in general, and in particular to an apparatus for altering bits within an instruction. Still more particularly, the present invention relates to an apparatus for adjusting a STORE instruction having memory hierarchy control bits.
2. Description of the Prior Art
Typically, Reduced Instruction Set Computing (RISC) processors have fewer instructions than their Complex Instruction Set Computing (CISC) counterparts. Thus, to a certain extent, RISC technology simplifies the task of writing compilers for processors that utilize a RISC instruction set. Moreover, from a processor design standpoint, focus can be placed on implementing and optimizing those important and frequently-used instructions rather than having some complex but seldom-used instructions constrain the maximum operating efficiency. Because of the above-mentioned reasons and others, RISC processors are gaining popularity among workstation and even some lower-end computer manufacturers.
For RISC processors, it is common that very few instructions are actually memory access instructions. In fact, some implementations may have only two instructions, LOAD and STORE, that access memories. Typically, a few specialized “atomic” operations may also be supported by the RISC processor for synchronization and memory updates via concurrent processes. Even in such cases, LOAD and STORE instructions are by far the most frequently-used memory access instructions for RISC processors. The execution of a LOAD instruction will cause a processor register to be written with data associated with in a specified main memory address. Conversely, the execution of a STORE instruction will cause data resident in a processor register to be written to a memory hierarchy in association with a main memory address. The present disclosure provides an apparatus for adjusting control bits within a STORE instruction.
SUMMARY OF THE INVENTION
A multiprocessor data processing system includes a multi-level memory hierarchy. In accordance with a preferred embodiment of the present invention, an apparatus for adjusting control bits within an instruction to be utilized within the multi-level memory hierarchy comprises a performance monitor and a bit adjuster. The memory hierarchy control bits indicates a memory level within the multi-level memory hierarchy to which an updating operation should be applied. In response to the outputs from the performance monitor, the bit adjuster alters at least one of the memory hierarchy control bits within the instruction in order to achieve optimal performance for the updating operation.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4429363 (1984-01-01), Duke et al.
patent: 5386547 (1995-01-01), Jouppi
patent: 5579493 (1996-11-01), Kiuchi et al.
patent: 5623627 (1997-04-01), Witt
patent: 5721864 (1998-02-01), Chiarot et al.
patent: 5724549 (1998-03-01), Selgas et al.
patent: 5774685 (1998-06-01), Dubey
patent: 5809522 (1998-09-01), Novak et al.
patent: 5829038 (1998-10-01), Merrell et al.
Arimilli Ravi Kumar
Dodson John Steve
Guthrie Guy Lynn
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Robertson David L.
Salys Casimer K.
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