Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-05-13
2001-07-10
Nelms, David (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
36, C438S010000
Reexamination Certificate
active
06260180
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to computer-aided circuit design systems, and more particularly to a system and method for evaluating a netlist file and detecting FETs that are susceptible to bootstrapping or charge pumping.
2. Discussion of the Related Art
Integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and other components on a single semiconductor “chip” in which the components are interconnected to perform a given function such as a microprocessor, programmable logic device (PLD), electrically erasable programmable memory (EEPROM), random access memory (RAM), operational amplifier, or voltage regulator. A circuit designer typically designs the integrated circuit by creating a circuit schematic indicating the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and ensure performance goals are satisfied.
In the world of electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer aided design (E-CAD) tools. As will be appreciated, electronic devices include electrical analog, digital, mixed hardware, optical, electro-mechanical, and a variety of other electrical devices. The design and the subsequent simulation of any circuit board, VLSI chip, or other electrical device via E-CAD tools allows a product to be thoroughly tested and often eliminates the need for building a prototype. Thus, today's sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools must deal with an electronic representation of the hardware device. A “netlist” is one common representation of a hardware device. As will be appreciated by those skilled in the art of hardware device design, a “netlist” is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often a netlist will contain a number of circuit “modules” which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules essentially containing no boundary differentiation between the circuit modules and other components in the device. By way of analogy, one graphical representation of a flat netlist is simply the complete schematic of the circuit device.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module which may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist would show the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules would be represented by “black boxes.” As will be appreciated by those skilled in the art, a black box is a system or component whose inputs, outputs, and general function are known, but whose contents are not shown. These “black boxes” representations, hereinafter called “modules”, will mask the complexities therein, typically showing only input/output ports.
An integrated circuit design can be represented at different levels of abstraction, such as the Register-Transfer level (RTL) and the logic level, using a hardware description language (HDL). VHDL and Verilog are examples of HDL languages. At any abstraction level, an integrated circuit design is specified using behavioral or structural descriptions or a mix of both. At the logical level, the behavioral description is specified using boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are full-adders, NAND gates, latches, and D-Flip Flops.
Having set forth some very basic information regarding the representation of integrated circuits and other circuit schematics through netlists, systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally such systems operate by identifying certain critical timing paths, then evaluating the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
One such system known in the prior art is marketed under the name PathMill, by EPIC Design Technology, Inc. (purchased by Synopsys). PathMill is a transistor-based analysis tool used to find critical paths and verify timing in semiconductor designs. Using static and mixed-level timing analysis, PathMill processes transistors, gates, and timing models. It also calculates timing delays, performs path searches, and checks timing requirements. As is known, PathMill can analyze combinational designs containing gates, and sequential designs containing gates, latches, flip-flops, and clocks. Combinational designs are generally measured through the longest and shortest paths.
While tools such as these are useful for the design verification process after layout, there are various circuit characteristics, attributes, or configurations that are not identified and/or addressed in the PathMill product and other similar products. For example, there is often a need to evaluate a circuit to detect a wide variety of potential design pitfalls. Certain pitfalls may apply to all designs, while certain other pitfalls may apply only to certain designs. One potential circuit pitfall relates to design configurations where bootstrapping, or charge pumping occurs. As is known, bootstrapping (or charge pumping) occurs when a node voltage exceeds VDD (the supply voltage). Although there are certain situations in which bootstrapping is desired, many times it can have undesirable consequences on circuit operation.
Therefore, it would be desirable to provided an automated tool that can evaluate a netlist file of a large circuit design to identify particular circuit configurations that may result in bootstrapping.
SUMMARY OF THE INVENTION
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The present invention is generally directed to a system and method for evaluating a netlist of a schematic to detect circuit configurations that are susceptible to bootstrapping. In accordance with one aspect of the present invention, a method is provided for detecting n-type field effect transistors (NFETS) that are susceptible to bootstrapping. The method operates by evaluating at least one NFET in a netlist and ensuring that the at least one NFET is not channel connected to ground. The method further ensures that a gate node of the at least one NFET is connected to a channel node of a PFET.
In accordance with a similar aspect of the present invention, a method is provided for detecting p-type field effect transistors (PEETs) that are susceptible to bootstrapping. The method operates by evaluating at least one PFET in a netlist and ensuring that the at least one PFET is not channel connected to VDD. The method further ensures that a gate node of the at least one PFET is connected to a channel node of a NFET.
REFERENCES:
patent: 4907180 (1990-03-01), Smith
patent: 5790415 (1998-08-01), Pullela et al.
patent: 5880967 (1999-03-01), Jyu e
Hewlett--Packard Company
Le Thong
Nelms David
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