Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-08-26
2001-09-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06292914
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory, particularly to a nonvolatile memory having functions of electrically rewriting and of verifying data stored therein.
2. Description of the related art
For a semiconductor memory, there are a random access memory capable of freely reading and writing data and a read only memory used specifically for reading data which is written in advance. The read only memory is generally composed of a nonvolatile semiconductor memory. For the read only memory, there is a type capable of electrically rewriting data. Such a memory includes a memory capable of erasing data at a time, namely, by the batch.
The memory capable of electrically rewriting data includes a type having a function of verifying whether a threshold voltage of a memory cell on which data is written is a given voltage or not when given data is written (sometimes called programmed) on a memory cell array composed of a plurality of memory cells incorporated in this memory.
A verification processing using this verification function is executed, for example by a program processing of given data. The verification processing is executed every time given data is written on a memory cell. If it is detected in the verification processing that a memory cell on which data is written does not reach a given threshold, the program processing and verification processing are executed again. Until a memory cell on which data is written reaches a given threshold voltage, the given number of program processing and verification processing are repeatedly executed. If the given number of verification processing is executed and a memory cell on which data is written does not reach a given threshold voltage, program processing is terminated by designating a failure in the program processing.
A demand for representing the maximum value of time needed for a program processing has been recently increased with a warranty of manufacturers of memories. However, the maximum value of time is differentiated depending on the memories and how may times the program processing and verification processing are executed, thus impacting on the termination of the program processing. Accordingly, it scarcely occurs that all memories can execute the preset given number (the maximum number) of program processing and verification processing. Accordingly, it is required that the maximum value of time needed for executing program processing, namely, the time when the preset given number of program processing and verification processing are executed can be measured.
Further, memory has progressed to a high degree of integration, and thus miniaturization of chip size. Accordingly, it is necessary to avoid the sharp increase of the number of circuit configurations in order to measure the maximum value of time needed for executing the program processing. It is further necessary not to impede a normal operation of a memory by a circuit capable of measuring the maximum value of time needed for programming data.
It is another object of the invention to provide a semiconductor memory capable of attaining the above object without sharply increasing the number of circuit configurations.
It is still another object of the invention to provide a semiconductor memory capable of attaining the above object without impeding a normal operation of the memory.
SUMMARY OF THE INVENTION
To achieve the above objects, a semiconductor memory capable of verifying data stored therein according to the invention comprises a memory cell array comprising a plurality of memory cells in which given data can be stored, a verification circuit for verifying data stored in the memory cell array and outputting a fit signal for instructing the result of verification, a control signal output circuit for receiving the fit signal and outputting a second control signal having a voltage level which is selectively controlled to a voltage level corresponding to a voltage level of the fit signal or a first voltage level in response to a first control signal, and a counter for counting the number of verification processing of data by the verification circuit, wherein the counter is capable of updating the number of verification processing if a voltage level of a count signal is in the first voltage level.
Further, the semiconductor memory of the invention may include a write control circuit for outputting a write signal for instructing writing of data on the memory cell array, wherein the write control circuit continues to write data on the memory cell array when the second control signal is in the first voltage level.
Further, the semiconductor memory of the invention may have a status instruction circuit for outputting a signal representing an output status of the write signal.
Further, the semiconductor memory of the invention may be structured that the control signal output circuit includes a logic circuit for receiving the first control signal and the fit signal, wherein the logic circuit outputs a signal for rendering a voltage level of the second control signal to be the first voltage level when a voltage level of the first control signal is the second voltage level, and for rendering a voltage level of the second control signal to be a voltage level corresponding to a voltage of the fit signal when the voltage level of the first control signal is a third voltage level.
Further, the semiconductor memory of the invention may be structured that the counter outputs an instruction signal for instructing that the count value exceeds preset given number, and the write control circuit is controlled by the instruction signal.
Further, the semiconductor memory of the invention may be structured that the generation circuit can change the voltage level of the first control signal when the semiconductor memory is powered on.
Further, the semiconductor memory of the invention may be structured that the control signal output circuit includes a generation circuit for generating the first control signal, wherein the generation circuit generates a first control signal having a given voltage level in response to the selected signal.
Further, the semiconductor memory of the invention may be structured that the generation circuit can change the voltage level of the first control signal when the semiconductor memory is powered on.
Further, the semiconductor memory of the invention may be structured that the first control signal is inputted from one of pads provided in a semiconductor chip constituting the semiconductor memory, wherein the pad is not connected to an external terminal in a packaged state.
Further, the semiconductor memory of the invention may be structured that the semiconductor memory has a status instruction circuit for outputting a signal representing an output status of the write signal.
Further, the semiconductor memory of the invention may be structured that the status signal is connected to a terminal provided on the semiconductor memory.
Further, the semiconductor memory of the invention may be structured that the counter counts based on a status of a signal outputted from the write control circuit when writing data.
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De'cady Albert
Jones Volentine PLLC
OKI Electric Industry Co., Ltd.
Torres Joseph
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