Multi-level, split-gate, flash memory cell

Details Multi-level, split-gate, flash memory cell Multi-level, split-gate, flash memory cell

1998-11-24

2001-08-28

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S316000, C257S320000, C257S321000, C257S322000

Reexamination Certificate

active

06281545

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to flash memory devices.
2. Description of Related Art
U.S. Pat. No. 5,414,287 of Hong for “Process for High Density Split-Gate Memory Cell for Flash or EPROM”; U.S. Pat. No. 5,494,838 of Chang for “Process of Making EEPROM Memory Device Having A Sidewall Spacer Floating Gate Electrode” and U.S. Pat. No. 5,364,806 of Ma for “Method of Making a Self-Aligned Dual-Bit Split Gate (DSG) Flash EEPROM Cell” show various methods/structures for split-gate Flash or EPROM cells.
SUMMARY OF THE INVENTION
An object of this invention is a multi-level storage cell which increases the density of flash memory devices.
In accordance with this invention, the features are provided, as follows:
1. The single cell provides multi-level storage information.
2. The device has a split-gate structure.
3. Each cell has plural, separated floating gate structures. In particular two floating gate electrodes are located under one control gate electrode so that multi-level storage is achieved by a double split-gate structure.
4. The multi-level storage cell is controlled by charge stored in two separated, individual floating gate electrodes.
5. The multi-level storage cell is fabricated using an ETOX (EPROM with Tunnel OXide) process.
In accordance with another aspect of this invention, a semiconductor memory device comprises the following. A tunnel oxide layer is formed over a doped semiconductor substrate. A doped first polysilicon layer has a thickness of about 1,500 Å formed over the tunnel oxide layer, and the first polysilicon layer is patterned into a pair of floating gate electrodes. A first dielectric layer overlies the top of the floating gate electrodes and is present on the sidewalls thereof, the and the exposed edge of the tunnel oxide layer which lies below the floating gate electrodes. The first dielectric layer also covers the substrate, where it is exposed, aside from the floating gate electrodes. There is a second polysilicon layer overlying the first dielectric layer. A tungsten silicide layer overlies the second polysilicon layer. A second dielectric layer overlies the device covering the tungsten silicide layer. A control gate electrode spans across the pair of floating gate electrodes formed of the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes. There are source/drain regions in the substrate self-aligned with the control gate electrode.
Preferably, the control gate electrode and the floating gate electrodes are patterned into a split-gate structure. The device includes separate floating gate structures with two floating gate electrodes under one control gate electrode. The tunnel oxide layer has a thickness of from about 80 Å to about 100 Å. The first dielectric layer comprises a silicon Oxide/Silicon Nitride/Silicon Oxide (ONO) in a layer having a thickness of from about 150 Å to about 200 Å.
The second polysilicon layer has a thickness of from about 1000 Å to about 2000 Å. The silicide layer has a thickness of from about 1000 Å to about 2000 Å. There is a dielectric cap over the silicide layer formed of silicon dioxide. There are Medium Doped Drain (MDD) ion implanted regions of dopant in the MDD regions in the substrate with a concentration of from about 1×10
18
atoms/cm
3
to about 5×10
19
atoms/cm
3
. There are silicon dioxide spacers formed adjacent to the sidewalls. The source/drain ion implanted regions ions are self-aligned with the gate electrode stack which after annealing have a concentration of from about 1×10
19
atoms/cm
3
to about 1×10
20
atoms/cm
3
of dopant in the source/drain regions the substrate.
There are program, erase, and read voltages employed for the cell operation of the device, which are as follows:
Program
Erase
FG1
FG2
FG1
FG2
Read
V
G
8 V
12 V 
−5 V  
−5 V  
5 V
VS
5 V
0 V
5 V
0 V
0 V
V
D
0 V
5 V
0 V
5 V
2 V
Thus, operation of the device is controlled in this way.
Preferably, the multi-level storage is controlled by charge stored in two separated floating gate electrodes.


REFERENCES:
patent: 5364806 (1994-11-01), Ma et al.
patent: 5414287 (1995-05-01), Hong
patent: 5494838 (1996-02-01), Chang et al.
patent: 5925906 (1999-07-01), Tanaka
patent: 5929479 (1999-07-01), Oyama
patent: 5929480 (1999-07-01), Hisamune
patent: 6111287 (2000-08-01), Arai

Affiliated with

Also associated with

Rating

Multi-level, split-gate, flash memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-level, split-gate, flash memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-level, split-gate, flash memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2525188