Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-05-04
2001-07-24
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000, C257S332000, C257S301000, C257S302000, C257S304000, C438S270000, C438S271000
Reexamination Certificate
active
06265744
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a trench structure and a method for manufacturing the same. More specifically, the present invention relates to a gate contact structure of a MOSFET (insulated-gate electric field transistor) in which a side wall of a trench serves as a channel region or an IGBT (insulated-gate bipolar transistor), and a method for manufacturing the structure.
Conventionally a semiconductor device including a number of trench MOSFETs in which a side wall of a trench serves as a channel region, arranged in parallel on a semiconductor substrate (referred to as a U-MOS hereinafter) and a semiconductor device including a number of trench IGBTs arranged in parallel on a semiconductor substrate (referred to as a U-IGBT hereinafter), have been known.
FIGS. 1A
to
1
D schematically show pattern structures of a prior art U-MOS to be manufactured.
FIG. 1A
illustrates a source pattern
101
and a base pattern
103
of the U-MOS,
FIG. 1B
shows a trench pattern
105
thereof,
FIG. 1C
shows a gate electrode leading pattern
107
thereof, and
FIG. 1D
illustrates a contact forming pattern
109
thereof.
FIG. 2A
schematically shows the status of the prior art U-MOS subsequent to a step of making a contact hole based on the contact forming pattern
109
in the manufacturing process of the prior art U-MOS.
FIG. 2B
is a schematic cross-sectional view taken along line
2
B—
2
B of
FIG. 2A
, and
FIG. 2C
is a schematic cross-sectional view taken along line
2
C—
2
C of FIG.
2
A.
An outline of the manufacturing process of the above prior art U-MOS will now be described. First, based on the source pattern
101
and base pattern
103
shown in
FIG. 1A
, a source region
125
and a base region
123
are formed in a surface area of a semiconductor substrate (drain region)
121
.
Next, based on the comb trench pattern
105
shown in
FIG. 1B
, a number of trenches
127
are formed in the source region
125
to a depth reaching the drain region
121
. After that, a gate insulation film
129
is formed on the inner wall of each of the trenches
127
and on the surface of the semiconductor substrate. In order to form a gate electrode leading portion (which will be described later) in part of the base region
123
, the trenches
127
are not formed in the part of the base region
123
. In other words, the trench pattern
105
is partly missed.
Thereafter, polysilicon
131
is buried into each of the trenches
127
and deposited on the entire surface of the semiconductor substrate including the surface of the gate insulation film
129
. The polysilicon
131
is then thermally treated or the impurities introduced into the polysilicon are activated by the thermal treatment.
After that, based on the gate electrode leading pattern
107
shown in
FIG. 1C
, the thermally-treated polysilicon
131
is patterned to form a pad
133
for contact through which a gate electrode is led to the missing portion of the trenches
127
and, at the same time, to etch back the top surface of the polysilicon
131
buried into the trenches
127
.
An interlayer insulation film
135
is deposited on the entire surface of the semiconductor substrate and then a large contact hole
137
for leading the gate electrode is formed in the interlayer insulation film
135
formed on the pad
133
. Simultaneously, a number of source/base leading contact holes
139
are formed in the interlayer insulation film
135
in the peripheral portions of the trenches
127
and its underlying gate insulation film
129
.
After that, as illustrated in
FIGS. 3A and 3B
, a metal wiring layer (e.g., aluminum wiring layer) is formed on the whole surface of the semiconductor substrate by sputtering and subjected to necessary patterning to form both a source/base electrode
141
and a gate electrode
143
.
Moreover, a drain electrode
145
is formed on the underside of the semiconductor substrate to complete the U-MOS.
FIG. 4
illustrates an equivalent circuit of the above-described prior art U-MOS having a trench structure. Using this U-MOS, a source S and a back gate (base region) BG are grounded, and a voltage of not higher than 100V is applied to a drain D while a voltage of not higher than 30V is applied to a gate G.
The foregoing manufacturing process of the prior art U-MOS, however, has the following problem. An extra exposure step of forming the pad
133
is required in addition to an exposure step associated with PEP (photoengraving process) for making a gate electrode leading contact hole
137
in the interlayer insulation film
135
, and the number of manufacturing steps is increased accordingly.
Furthermore, the prior art U-MOS has the following problem. An electric field is concentrated upon a trench corner portion (indicated by A in FIG.
3
B), which is extracted from inside the trench
127
and led to the pad
133
, and the gate insulation film
129
is decreased in reliability.
The same problems as described above are caused in the prior art U-IGBT.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of reducing the number of manufacturing steps and preventing an electric field from concentrating on a trench corner portion to improve the reliability of a gate insulation film, and a method for manufacturing the same semiconductor device.
In order to attain the above object, according to a first aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate of a first conductivity type serving as a drain region of a MOS transistor, a base region of the MOS transistor formed in a surface area of the semiconductor substrate and constituted of a semiconductor layer of a second conductivity type, a source region of the first conductivity type and a gate leading region of the first conductivity type both formed in a surface area of the base region separately from each other, a trench section formed in the source region and the gate leading region to such a depth as to penetrate the base region, a gate insulation film formed on an inner wall of the trench section and a surface of the semiconductor substrate, polysilicon buried into the trench section and thermally treated, an interlayer insulation film deposited on the semiconductor substrate, and a gate electrode contacting both the gate leading region and the polysilicon in the trench section in the gate leading region through a gate electrode contact hole corresponding to the gate leading region and formed in the interlayer insulation film and the gate insulation film formed thereunder.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a base region of a second conductivity type in a surface area of a semiconductor substrate of a first conductivity type, forming both a source region of the first conductivity type and a gate leading region of the first conductivity type in a surface area of the base region separately from each other, forming a trench section in the source region and the gate leading region to such a depth as to penetrate the base region, burying polysilicon into the trench section with a gate insulation film interposed therebetween, thermally treating the polysilicon, and then etching back an entire surface of the polysilicon in the trench section until a top surface of the polysilicon becomes lower than a surface of the semiconductor substrate, depositing an interlayer insulation film on an entire surface of the semiconductor substrate with the gate insulation film interposed therebetween and then forming a gate electrode contact hole, which corresponds to the gate leading region, in the interlayer insulation film and the gate insulation film formed thereunder, and forming a gate electrode contacting both the gate leading region and the polysilicon in the trench section in the gate leading region through the gate electrode contact hole.
According to a third aspect of the present invention
Fenty Jesse A
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Saadat Mahshid
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