Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-01-16
2001-08-07
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S379000, C257S306000, C257S903000, C257S904000, C365S051000, C365S154000, C365S156000
Reexamination Certificate
active
06271569
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device having memory cells and a method of manufacturing the same.
2. Description of the Background Art
An SRAM (Static Random Access Memory) is a known kind of volatile semiconductor device. In the SRAM, memory cells are arranged at crossings between complementary type data lines (bit lines) and word lines which are arranged in a matrix form (i.e., in rows and columns).
FIG. 59
is an equivalent circuit diagram showing a memory cell in a conventional SRAM.
FIG. 60
shows a planar layout of the memory cell in the conventional SRAM. Referring to
FIGS. 59 and 60
, the memory cell in the conventional SRAM is formed of two access transistors A
1
and A
2
, two driver transistors D
1
and D
2
and two high-resistance load elements R
1
and R
2
.
Two high-resistance load elements R
1
and R
2
and two driver transistors D
1
and D
2
form a flip-flop circuit. This flip-flop circuit forms two cross-coupled storage nodes N
1
and N
2
. Storage nodes Ni and N
2
have bistability of High (N
1
) and Low (N
2
) or bistability of Low (N
1
) and High (N
2
). This bistable state is kept as long as the nodes are supplied with a predetermined power supply voltage.
One of source/drain regions of each of access transistors A
1
and A
2
is connected to storage node N
1
or N
2
which is an I/O terminal of the flip-flop circuit. The other source/drain region of each of access transistors A
1
and A
2
is connected to the bit line. Gate electrodes of access transistors A
1
and A
2
are connected to the word line. The word line control on/off of access transistors A
1
and A
2
.
A drain region of each of driver transistors D
1
and D
2
is connected to one of source/drain regions of access transistor A
1
or A
2
. Source regions of driver transistors D
1
and D
2
are connected to a GND line (VEE line). The gate is electrode of driver transistor D
1
is connected to the source/drain region of access transistor A
2
. The gate electrode of driver transistor D
2
is connected to the source/drain region of access transistor A
1
. High-resistance load elements R
1
and R
2
are connected to source/drain regions of access transistors A
1
and A
2
, respectively. High-resistance load elements R
1
and R
2
are also connected at their other ends to a power supply line (Vcc line).
In an operation for writing data, word line (WL) is selected to turn on access transistors A
1
and A
2
. In accordance with a desired logical value, a voltage is forcedly applied to the bit line pair, so that the flip-flop circuit is set to either of the foregoing bistable states.
For reading data, access transistors A
1
and A
2
are turned on. Potentials on storage nodes N
1
and N
2
are transmitted onto the bit lines.
Nowadays, there is a tendency to reduce an areas occupied by memory cells in the SRAM for reducing the cost, as is also desired in other devices. With reduction in occupied area of the memory cells, however, deterioration of a resistance against soft error becomes more manifest. The “soft error” represents the following phenomenon. Electrons and hole pairs are generated by incident alpha-rays passed through a package material and others, and the electrons are attracted toward the storage nodes of memory cells. Therefore, storage information of the memory cell is inverted to cause a random error. This error is called the soft error. As the area occupied by the memory cell decreases, a storage capacity C of the storage node portion in the memory cell decreases. Therefore, the quantity of charges (Q=CxV) which can be accumulated in the storage node part also decreases. Reduction in charges accumulated in the storage node portion results in a problem that the soft error is more liable to occur.
FIG. 61
shows a planar layout of polycrystalline silicon and active regions at a first level or layer in the conventional memory cells shown in FIG.
60
.
FIG. 62
is a planar layout of polycrystalline silicon at a second level. Referring to
FIGS. 61 and 62
, there are shown two memory cells which are symmetrical with respect to a line and are arranged along word lines
105
a
and
105
d
. According to the layout of polycrystalline silicon layers
111
a
-
111
f
at the second level, two high-resistance portions
111
a
of a neighboring memory cells each have one end connected to a common Vcc interconnection
111
f
. Therefore, a region surrounded by two high-resistance portions
111
a
and Vcc interconnection
111
f
is closed at its one end and has a dead-lane form. As is well known, the pattern in the dead-lane form causes such a problem that a portion of a photoresist near the closed end cannot be accurately patterned without difficulty.
More specifically, a pattern having a rapidly changed portion such as a pattern closed at one end causes reduction in resolution of an optical focusing system, because the optical focusing system cannot accurately transfer such a rapid change. When patterning is performed to produce a form having a rapidly changed portion such as a closed portion, therefore, patterned high-resistance portion
111
a
has an excessively large width at a portion requiring a rapidly changed pattern as shown in FIG.
62
. More specifically, as shown in
FIG. 62
, high-resistance portion
111
a
disadvantageously has an excessively large width WHE near a closed end (base end), so that a resistance value of high-resistance portion
111
a
decreases.
For overcoming the above problem, high-resistance portion
111
a
must have a large length LHR. If high-resistance portion
111
a
has larger length LHR, storage node portion
111
c
in the memory cell of the same size has a smaller length L
NODE
. As a result, storage node portion
111
c
has a smaller planar area, and therefore has a smaller capacity. The small capacity of the storage node portion
111
c
causes a problem that the soft error is liable to arise as already described.
In the conventional layout shown in
FIG. 62
, a distance D
1
is required between storage node portions
111
c
of the neighboring memory cells, and for this purpose, a distance of half the minimum processable size or more must be kept with respect to the boundary between the neighboring memory cells. This restricts an allowable maximum value of width W
NODE
of storage node portion
111
c
. This also prevents easy increasing of the capacity of storage node portion
111
c.
According to the planar layout of the memory cells in the conventional SRAM shown in
FIGS. 60
to
62
, it is difficult to provide a large area of storage node portion
111
a
as already described, and consequently it is difficult to increase the capacity of storage node portion
111
c
. Therefore, it is difficult to improve a resistance against soft error if the size of memory cell is reduced.
If two neighboring memory cells are arranged symmetrically with respect to a line as shown in
FIG. 61
, an appropriate distance D
3
must be kept between gate electrodes
105
c
of two driver transistors of the neighboring memory cells. As a result, it is difficult to reduce a space between the neighboring memory cells.
In the conventional planar layout shown in
FIGS. 60 and 61
, a GND region
108
d
and a word line
105
d
are overlapped with each other in a plan view. Due to this, a large parasitic capacity is present between word line
105
d
and GND region
108
d
, so that a large RC delay occurs on word line
105
d.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor device which can improve a resistance against soft error even if memory cells have a reduced size.
Another object of the invention is to provide a semiconductor device which can remarkably increase a storage capacity of a storage node portion.
Still another object of the invention is to provide a semiconductor device which can improve a resistance against soft error and can reduce an RC delay on a word line.
Yet another object o
Honda Hiroki
Ishigaki Yoshiyuki
McDermott & Will & Emery
Mintel William
Mitsubishi Denki & Kabushiki Kaisha
Nadav Ori
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