Method to improve the uniformity of chemical mechanical...

Details Method to improve the uniformity of chemical mechanical... Method to improve the uniformity of chemical mechanical...

1998-12-16

2001-09-04

Nguyen, Tan T. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S626000, C438S631000, C438S634000, C438S637000, C438S692000, C438S926000

Reexamination Certificate

active

06284647

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method for fabricating semiconductor integrated circuits (ICs), and more particularly to a chemical mechanical polishing process (CMP) for forming the semiconductor integrated circuits.
2. Description of the Related Art
CMP is now a common and the most reliable technique today for applying in global planarization in very large scale integrated circuits and even in ultra large scale integrated circuits. Therefore, it is of great interest to develop and to improve the CMP technique in order to cut down the cost.
As the IC devices are continuously sized down to a line width of 0.25 &mgr;m or even 0.18 &mgr;m (deep sub-half micron), employing CMP to planarize the wafer surface, especially to planarize the oxidized surface of the shallow trench, becomes more important. If the opening of the trench is larger than A
1
, there is a dish formed on the oxide layer in the position of the layer trench from the hardness of the oxide layer which is softer than other materials. The result is called as “dishing effect”.
FIGS. 1A-1D
are cross-sectional views showing a conventional process of forming a shallow trench isolation structure incorporating CMP technique. As shown in
FIG. 1A
, a pad oxide layer
101
is formed on a provided substrate
100
. A dielectric layer
102
on the pad oxide layer
101
. Active areas
103
are divided by trenches after photolithography and etching process.
In
FIG. 1B
, a oxide layer
104
is formed in the trenches between the active areas
103
and to overflow the dielectric layer
102
using Chemical Vapor Deposition (CVD). The oxide layer
104
is polished by CMP using the dielectric layer
102
as a stop layer. Shallow trench isolation structures
105
and
106
are thus formed in the substrate
100
as shown in FIG.
1
C.
As shown in
FIG. 1D
, the dielectric layer
102
remaining on the active areas
103
of the substrate
100
is removed to complete the shallow trench isolation structures. In follow-up steps, a gate oxide layer
107
and a polysilicon layer
108
are formed on the substrate
100
to form a metal-oxide semiconductor (MOS) transistor or other devices.
Sizes of the trenches between the active areas
103
may be different. As shown in
FIG. 1C
, the STI structure
106
is larger than the STI structure
105
. The top surface of the STI structure
105
is planar, but the top surface of the STI structure
106
is dishing. To prevent the dishing effect occurring at the surface of a large trench during CMP process and to obtain a superior CMP uniformity, a dummy mesa was proposed, incorporated with the CMP technique. The dummy mesa is used as a polishing stop layer within the large trench while the CMP process being performed.
However, there are active area regions with different integration used for different objects on a chip. Simply forming dummy mesas within the large STI structure between the active areas cannot effectively adjust the integration of the global substrate, because the integration of the different active area regions, especially used for memory manufactures such as static random access memory (SRAM) or dynamic random access memory (DRAM), are not the same. Therefore, according to the conventional process, the uniformity of the CMP process can not be controlled effectively.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of enhancing a chemical mechanical polishing uniformity. According to the present invention, the positions of dummy mesas are determined by the integration of different active area regions for different circuit regions on a substrate to make the integrations thereof being the same on the global chip. Therefore, the dishing effect during CMP process can be effectively decreased.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, this invention provides a method of enhancing chemical mechanical polishing uniformity. In the fabrication of a shallow trench isolation structure, there are active area regions with different integration formed in a chip. The integration of these active area regions in the chip is computed according circuit designs by a computer program analysis. One of the active area regions with the highest density is used as a basis, dummy mesas are formed in the other active regions according a comparing result from analysis to adjust the integration of the chip.


REFERENCES:
patent: 5492858 (1996-02-01), Bose et al.
patent: 5885856 (1999-03-01), Gilbert et al.
patent: 6109775 (2000-08-01), Tripathi et al.
patent: 6130457 (2000-10-01), Yu et al.

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