Semiconductor memory device with redundancy function

Details Semiconductor memory device with redundancy function Semiconductor memory device with redundancy function

1999-06-23

2001-07-17

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S222000, C365S225700, C365S230030

Reexamination Certificate

active

06262923

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with remedying means for defective memory cells.
2. Description of the Related Art
A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) is provided with respective memory cells at intersection points of a plurality of pairs of bit lines and a plurality of word lines. In this semiconductor memory device, the word line is selected with a row address and the pair of bit lines is selected with a column address to thereby allow the stored information of an intended memory cell to be read.
A conventional semiconductor memory device such as a DRAM employs a scheme of dividing a storage area into a plurality of blocks for an increased storage capacity or due to limitations on the length of the pair of bit lines.
For reading stored information stored in a memory cell of a semiconductor memory device comprising such a plurality of blocks, a row address is first specified, then a column address is specified and a block address must be specified. After the addresses are specified, a command is provided from the outside, thereby performing various operations such as data writing or reading.
However, even if the semiconductor memory device comprises a plurality of blocks as described above, there exists a problem that an increased storage capacity and an increased number of blocks require a long time for reading the stored content when one block can not be processed while another block is being processed.
For solving this problem, a synchronous DRAM and the like have come into use in which memory cells are divided into banks which can operate independent of each other, not dividing the memory cells into a plurality of blocks.
Within each bank, a group of memory cells specified with an address signal applied from the outside are activated. At this time, respective banks can be simultaneously in an activated state. The addresses of the group of memory cells to be activated are independent among the respective banks.
FIG. 1
shows a configuration of a conventional semiconductor memory device comprising such a plurality of banks.
In this figure, description is made assuming that the number of banks is two [bank A (ARRAY
0
) and bank B (ARRAY
1
)], the number of subarrays forming each bank is four (SA
00
to SA
03
, SA
10
to SA
13
, respectively), and the number of subword lines (not shown) included in each subarray is 512. Also, description is made here by using a hierarchy word lines structure. In this case, the number of the subword lines are eight for one main word line MWL. Thus, the row address of each bank comprises 11 bits (X
0
to X
10
). Each subarray in each bank is identified by bits X
9
, X
10
, each main word line in each subarray is identified by bits X
3
to X
8
, and each of eight subword line for one main word line is identified by bits X
0
to X
2
.
The replacement of a defective memory cell with a redundant memory cell is performed by two row addresses designated by bit X
0
. Each subarray has one redundant main word line RMWL (Redundant MWL) and eight subword lines connected thereto.
FIGS. 2A and 2B
show timing charts illustrating the operation of this conventional semiconductor memory device.
FIG. 2A
is a timing chart when the redundant memory cell is selected, while
FIG. 2B
is a timing chart when the redundant memory cell is not selected. ACT in
FIGS. 2A and 2B
denotes a signal indicating that a bank corresponding to each ACT is in an activated state, and is generated by a command decoder (not shown) and the like in response to a command input from the outside.
In
FIG. 1
, XADD comprising 11 bits is a row address signal and is fetched from the outside in accordance with ACT signal by an address buffer (not shown). XABF denotes a row address signal buffer circuit and generates complementary signals X
1
N to X
10
N, X
1
T to X
10
T in accordance with X
1
to X
10
within row address signals XADD. Respective redundant decoders XRED are circuits which store respective defective addresses to be replaced and perform storage/comparison for defective addresses.
FIG. 3
is a circuit diagram showing an example of redundant decoder XRED as described above. Redundant decoder XRED compares row address signal XADD and the defective address stored therein.
In this conventional semiconductor memory device, the replacement is made with two subword lines as a unit, so that X
1
to X
10
making up row address signal XADD are stored. Subword lines designated by X
0
, for example row address 0 and row address 1 are not distinguished within redundant decoder XRED and are determined as defective addresses when either of them is applied to redundant decoder XRED.
In redundant decoder XRED, the replacement address is stored by disconnecting either of fuses F
1
N to F
10
N or F
1
T to F
10
T. Although the way of disconnecting the fuse is not particularly limited, fusion with laser beam is commonly used. Disconnection of either FnN or FnT causes one bit of the replacement address to be stored. For example, when the relevant bit in the replacement address is 0 or 1, F
1
N to F
10
N are disconnected and F
1
T to F
10
T are not disconnected.
Next, the operation of redundant decoder XRED will be described. First, all of row address signal XADD go to a low level and redundant precharge signal PXR goes to a low level, thereby causing node
100
to go to a high level. Subsequently, based on an address signal applied from the outside, the states X
1
N to X
10
N and X
1
T and X
10
T are set within the complementary signals of 11 bits making up row address signal XADD. At this time, since XnN and XnT (n=1 to 10) are complementary signals, one of them is at a high level and the other is at a low level. For example, when the row address is 0 or 1, X
1
N to X
10
N are at a high level and X
1
T to X
10
T are at a low level. Thus, node
100
and node
101
are rendered conductive unless the replacement address stored in fuses FnN, FnT and row address signal XADD match.
Node
100
goes to a low level when redundant precharge signal PXR goes to a high level and the replacement address and row address signal XADD do not match, and node
100
remains at a high level when they match. Level at node
100
is held at node
102
in response to latch signal XLAT and outputted as defective address match signal XREBL.
FIG. 2A
shows a case where the replacement address and row address signal XADD match and defective address match signal XREBL at a high level is outputted.
FIG. 2B
shows a case where the replacement address and row address signal XADD do not match and defective address match signal XREBL at a low level is outputted.
When ACT signal goes to a low level, all defective address match signals XREBL are made unselected in response to XPRE signal as shown in
FIGS. 2A and 2B
, and therefore the selected redundant memory cell is made unselected.
FIG. 4
is a circuit diag ram showing an example of redundant memory cell selection circuit XRDN.
Redundant memory cell selection circuit XRDN exists on a one-to-one basis for each redundant row decoder RXDC. Since one redundant decoder XRED exists for two subword lines, one redundant memory cell selection
25
circuit XRDN exists for four redundant decoders XRED. This ratio is equal to the ratio of the number of the main word lines to the number of the subword lines. Redundant memory cell selection circuit XRDN, when one of four defective address match signals XREBL connected thereto goes to a high level, causes redundant replacement selection signal XRDNS set at a high level by a precharge circuit (not shown) to be pulled down to a low level. Redundant replacement selection signal XRDNS is a signal indicating that the redundant memory cell has been selected. Also, redundant memory cell selection circuit XRDN causes redundant row decoder selection signal RXDS to go to at a high level, and activates redundant row decoder RXDC connected on a one-to-one basi

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