Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-06-12
2001-09-04
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06286128
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit design tools. In particular, the present invention relates to integrated circuit design tools hat optimize area performance and signal integrity in integrated circuits.
2. Discussion of the Related Art
The interconnection wiring (“interconnect”) among circuit elements in an integrated circuit is expected to dominate signal delays and to limit achievable circuit density of an integrated circuit. Existing design methods, which treat interconnect as “parasitics” and focus on optimizing transistors and logic gates, are ill-equipped to provide a design that delivers the necessary performance. Typically, in a conventional design method, the circuit elements of an integrated circuit are first synthesized and placed. A global routing tool is then used to interconnect these circuit elements. Due to the interconnect dominance, accurate estimation of performance is available only after global routing. Because placement and routing are performed relatively independently, even though some tools take into consideration the connectivity among circuit elements in providing the placement, the global routing tool's ability to address power, timing, and congestion issues is severely limited.
Various techniques have been applied to address signal propagation performance in an integrated circuit design. For example, U.S. Pat. No. 5,638,291, entitled “Method and Apparatus for Making Integrated Circuits by Inserting Buffers into a Netlist to Control Clock Skew” to Li et al., discloses modification of a net list to insert buffers into clock signal paths to control clock skew. As another example, U.S. Pat. No. 5,396,435, entitled “Automated Circuit Design System and Method for Reducing Critical Path Delay Times” to Ginetti, discloses modification to a logic circuit to reduce delays in a critical path of an integrated circuit. However, the effectiveness of these methods for increasing circuit performance is constrained by their inability to concurrently affect placement of circuit elements.
Concurrent placement and wiring routing is disclosed in U.S. Pat. No. 4,593,363, entitled “Simultaneous Placement and Wiring for VLSI Chips” to Burstein et al. The '
363
patent discloses an iterative method in which a global router is invoked to route networks redistributed under a hierarchical placement algorithm.
SUMMARY OF THE INVENTION
The present invention provides a method for integrated circuit design that optimizes integrated circuit performance and signal integrity. In particular, a method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.
In one embodiment, the method further includes executing an inner loop (e.g., a geometrically bounded placement algorithm), the inner loop including the optimizing placement of the circuit elements, a reversal of optimizing logic changes that did not result in a change in the placement of the circuit elements, and the optimizing logic of the circuit elements; and executing an outer loop, the outer loop including executing a performance driven global router. The method can also include executing a final placement of the circuit elements, and executing a global router to perform a final routing.
The present invention is applicable not only to conventional design with conventional interconnect, but also in design, such as those with copper interconnect or design interconnected by RF transmission lines carrying high speed mixed mode signals. The present invention is also applicable to integrated systems design, such as the design of a micromachine including electronic circuits.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.
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Togawa et al. (“Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs with performance optimization”, proceedings of the ASP-DAC '95/CHDL '95/VLSI '95, IFIP international Conference on Hardware Description Languag, Aug. 1995.*
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Boyle Douglas B.
Chakraborty Abhijeet
Dunn Christopher
Gaitonde Dinesh
Gao Tong
Kik Phallaka
Kwok Edward C.
Monterey Design Systems, Inc.
Skjerven Morrill & MacPherson
Smith Matthew
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