Method for manufacturing electronic devices, comprising...

Details Method for manufacturing electronic devices, comprising... Method for manufacturing electronic devices, comprising...

1999-12-21

2001-08-14

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

C438S266000

Reexamination Certificate

active

06274411

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method for manufacturing electronic devices, and in particular non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions.
BACKGROUND OF THE INVENTION
The need has recently arisen in advanced processes (gate lengths of 0.35 &mgr;m or less), to integrate non-volatile memories of EEPROM type in high-speed devices that use the technique of saliciding of the diffusions. As known, this technique is based on the use of a self-aligned silicide layer (salicide), which reduces the resistivity of the junctions. The salicide layer (typically made of titanium, but also of cobalt or another transition metal) is produced by depositing a titanium layer on the entire surface of the device, and carrying out a heat treatment which makes the titanium react with the silicon, left bare on the junctions and the gate regions, such as to form titanium silicide. Subsequently, the non-reacted titanium (for example deposited on oxide regions) is removed by etching using a suitable solution, which leaves the titanium silicide intact. Thereby, both the gate regions and the junctions have a parallel silicide layer with low resistivity (approximately 3-4 &OHgr;/square), which reduces the resistance in series to the transistors. The salicide technique is described for example in the article “Application of the self-aligned titanium silicide process to very large-scale integrated n-metal-oxidesemi-conductor and complementary metal-oxide-semiconductor technologies”, by R. A. Haken, in
J. Vac. Sci. Technol. B
, vol. 3, No. 6, November/December 1985.
The high voltages necessary for programming non-volatile memories (higher than 16 V) are however incompatible with saliciding the diffusions of memory cells, since the breakdown voltage of salicided junctions is lower than 13 V.
Process flows that allow integration of non-volatile memory cells and high-speed transistors with saliciding have been produced; however, this integration is made difficult by the fact that these components have different characteristics, and require different process steps. The large number of necessary masks is also disadvantageous in these flows.
SUMMARY OF THE INVENTION
The disclosed embodiments of the present invention provide a manufacturing method with fewer masks than known methods. The method is simple and has the lowest possible costs.
According to the present invention, a method is provided for manufacturing electronic devices, and in particular non-volatile memory cells, HV transistors and LV transistors. In particular, the method includes forming LV gate oxide regions above first areas of a silicon substrate where low-voltage transistors are to be formed, HV oxide regions above second areas of the substrate where high voltage transistors are to be formed, selection oxide regions, tunnel oxide regions, and matrix oxide regions above third areas of the substrate where selection transistors and memory transistors of EEPROM cells are to be formed. The method further includes forming floating gate regions above the tunnel oxide regions and the matrix oxide regions; forming insulating regions above the floating gate regions; forming LV gate regions above the LV gate oxide regions; forming first source and drain regions laterally to the LV gate regions, which includes forming sacrificial spacers laterally to the LV gate regions, forming LV source and drain regions in the first areas in a self-aligned manner with the sacrificial spacers, the LV source and drain regions having a first doping level, removing the sacrificial spacers, and forming LDD regions laterally to the LV gate regions inside the first areas in a self-aligned manner with the LV gate regions, and the LDD regions, having a second doping level lower than the first level. Subsequently, the method also includes forming silicide regions on the LV source and drain regions and on the LV gate regions; forming semiconductor material regions completely covering the second and third areas; and forming HV gate regions above the HV oxide regions, selection gate regions above the selection oxide regions, and control gate regions above the insulating regions.


REFERENCES:
patent: 5024960 (1991-06-01), Haken
patent: 5472887 (1995-12-01), Hutter et al.
patent: 6010929 (2000-01-01), Chapman
patent: 6087211 (2000-07-01), Kalnitsky et al.
patent: 0 216 053 A2 (1987-04-01), None
patent: 0 811 983 A1 (1997-12-01), None
patent: 09283643 (1997-10-01), None
Wolf, Stanley and Richard N. Tauber,Silicon Processing for the VLSI Era, vol. 3, Lattice Press, Sunset Beach, California, 1986, pp. 608-611.
Shiba, Kazuyoshi and Katsuhiko Kubota, “Downscaling of Floating-gate EEPROM Modules for ASIC Applicatiuons,”Electronics and Communications in Japan, Part 2 75(12): 67-76, 1992.

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