Method for forming an interconnect structure

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S618000, C438S778000, C438S787000, C438S691000, C438S942000, C438S943000, C438S945000

Reexamination Certificate

active

06248659

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit fabrication, and more specifically to a method for forming an interconnect structure.
BACKGROUND OF THE INVENTION
The semiconductor industry continually strives to increase device performance by reducing the distance between individual devices, and by reducing the size of the devices themselves. Unfortunately, this continuing reduction in device dimensions has begun to adversely effect the performance and the reliability of integrated circuits. More specifically, as the device density increases more levels of metallization are required to interconnect the different devices. The plasma processes currently used to form the various levels of metallization, however, often damage the scaled devices. For example, the plasma processes currently used to etch contact or via openings often cause the thin gate oxide used in high performance semiconductor devices to rupture.
Accordingly, a need exists for a method to form interconnect structures which minimizes process induced damage to the integrated circuit.


REFERENCES:
patent: 5899737 (1999-05-01), Trabucco
patent: 0123456 A2 (2000-01-01), None
A Novel Technology to Form Air Gap for ULSI Application, by Chang et al., IEEE Electron Device Letters, vol. 20, No. 4, Apr. 1999, pp. 185-187.
Theoretical Study of Structural and Electronic Properties of H-Silsesquioxanes, by Xiang et al., J. Phys. Chem. B, vol. 102, No. 44, 1998, pp. 8704-8711.
Cage-rearrangement of silsesquioxanes, by Rikowski et al., Polyhedron vol. 16, No. 19, 1997. pp. 3357-3361.

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