Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-15
2001-06-26
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000, C257S321000, C257S622000
Reexamination Certificate
active
06252272
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of fabricating tho came.
In conventional semiconductor devices, impurity diffusion layers, gates, and contact holes, and so on are formed in a surface portion of a flat semiconductor substrate by using resist patterns.
FIG. 1
shows the sectional structure of a conventional MOS transistor. A drain
62
and a source
63
each made of an n-type impurity diffusion layer are formed at a predetermined interval in a surface portion of a flat p-type semiconductor substrate
61
. A gate electrode
65
is formed on the resultant surface via a gate oxide film
64
to form an n-channel fOS transistor
66
. In this conventional semiconductor device, however, the size of a fabricable transistor is unavoidably larger than the minimum processing size F corresponding to the limits of photolithography; generally, a size of 2F is necessary. For this reason, it is conventionally impossible to unlimitedly increase the degree of integration.
In conventional semiconductor devices as described above, elements are formed on the surface of a flat semiconductor substrate, and this requires a size larger than the minimum processing size F. So, the degree of integration cannot be increased.
Also, semiconductor memories have greatly improved with the recent micropatterning. However, straightforward development of conventional technology is against the trend to reduce a power consumption required by a high integration degree of LSIS. For example, in a non-volatile memory device, if an operating voltage was reduced with the reliability of a tunnel oxide film kept high, the efficiency of injection of electrons into a floating gate decreases.
For example, letting F be the minimum processing size in state-of-the-art general nonvolatile semiconductor memories, an element area of about 5.5F
2
is necessary even for a cell with the simplest cell structure and the minimum cell area. To write data by injecting electrons into the floating gate or erase data by extracting injected electrons from the floating gate of even a cell of this size, a very high electric field of, e.g., 18 V must be applied to cause FN tunneling in the tunnel oxide film.
Additionally, a strong electric field is applied not only to the tunnel oxide film between the substrate and the floating gate but also to an insulating film between the floating gate and the control gate. Therefore, to allow a tunnel current to flow only through the tunnel oxide film to make efficient data write or erase possible, the ratio of the thickness of the tunnel oxide film to that of the insulating film is adjusted to decrease the capacitive coupling ratio &ggr;(=C
1
/C
2
) of the capacitance C
2
of the tunnel oxide film to the capacitance C
1
of the insulating film. However, even when this is performed, the maximum operating voltage is still high, about 18 V, when data is written in or erased from conventional semiconductor memories.
On the other hand, in devices whose maximum operating voltage is as low as 12 V, the voltage required to write or erase data is decreased by using, e.g., channel hot electron injection. This, however, complicates the cell structure and takes the cell area very large, 11.5F
2
.
As described above, no conventional semiconductor memories can reduce the cell area and the maximum operating voltage at the same time.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device whose degree of integration can be increased and a method of fabricating the same.
It is another object of the present invention to provide a semiconductor device capable of achieving micropatterning and large reduction of the maximum operating voltage at the same time.
According to the present invention, a semiconductor device comprises, a serrated substrate whose surface is processed go that a section in a row direction is serrated that intervals between tops of peaks or between bottoms of valleys in the section are decreased to a minitmum processing size and the peaks and valleys alternately and repeatedly formed in the row direction of the surface extend in a column direction of the surface, a functional element including a thin linear gate formed to extend in the column direction in a valley via the insulating film and an impurity diffusion layer formed in two peaks on two sides of the valley in which the gate is formed, and a row-direction element isolation layer selectively formed in a valley by burying an insulating substance in the valley without forming a gate, the row-direction element isolation layer electrically isolating two functional elements arranged on two sides of the valley in the row direction.
The surface of a semiconductor substrate can be serrated in accordance with the minimum processing size. A gate formed in a valley and impurity diffusion layers formed in peaks on the two sides of the valley form a functional element. The impurity diffusion layers of this functional element are isolated from each other because the adjacent valley functions as an element isolation region. Since the functional element or the element isolation region is formed in a valley corresponding to the minimum processing size, the element area is reduced.
In a complementary semiconductor device of the present invention, the function element comprises a first-conductivity type functional element including impurity diffusion layers of a first conductivity type formed in first and second adjacent peaks, a second-conductivity type region in a first valley between the first and second peaks, and a first thin linear gate formed in the first valley in the column direction via the insulating film, and a second-conductivity type functional element including impurity diffusion layers of a second conductivity type formed in third and fourth adjacent peaks, a Legion of the first conductivity type in a second valley between the third and fourth peaks, and a second thin linear gate formed in the second valley in the column direction via the insulating film.
This device can further comprise, on the serrated substrate, a column-direction element isolation layer formed by burying an insulating substance in a trench linearly extending in the row direction and deeper than the valleys.
In this device, a direction in which a driving current flows in the functional element can be the row direction of the serrated substrate. This increases the driving current and reduces an occupied area of the functional element at the name time.
According to the present invention, a method of fabricating a semiconductor device comprises the steps of serrating a surface of a semiconductor substrate, on which an impurity diffusion layer is formed, in accordance with a minimum processing size to form peaks made of the impurity diffusion layer and valleys for separating the impurity diffusion layer, and selectively forming gates in predetermined valleys, wherein the impurity diffusion layer in peaks on two sides of a valley in which the gate is formed and the gate form a functional element in the valley in which the gate is formed, and a peak in which the gate is not formed is used as an element isolation region.
According to the present invention, a method of fabricating a semiconductor device by which the surface of a semiconductor substrate is serrated comprises the steps of doping an impurity into a surface portion of a semiconductor substrate to form an impurity diffusion layer, forming a mask material patterned into a predetermined shape at intervals equal to a minimum processing size on a surface of the impurity diffusion layer, anisotropically etching the surface portion of the semiconductor substrate by using the mask material as a mask to form V-shaped grooves deeper than the impurity diffusion layer, burying an insulating film in the grooves, removing the mask material to expose the surface of the semiconductor substrate, anisotropically etching the exposed surface portion of the semiconductor substrate not covered with the insulating film to for
Itoh Hitoshi
Uchida Ken
Watanabe Hiroshi
Crane Sara
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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