Salicide formation process

Details Salicide formation process Salicide formation process

1999-12-20

2001-08-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000, C438S301000

Reexamination Certificate

active

06277721

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of semiconductor devices incorporating structures including of a layer of polysilicon covered by a self-aligned layer of metal silicide.
2. Description of the Related Art
As line widths and geometries for semiconductor devices are made smaller, the polysilicon electrodes that form the gates of MOS devices and wiring lines within semiconductor devices become undesirably resistive. Multilayer electrodes in which a layer of polysilicon is covered by one or more layers of metals or metal silicides are used to provide electrodes having a lower resistance than electrodes consisting solely of polysilicon. Silicide electrodes may consist, for example, of a layer of polysilicon having a thickness of approximately 1000 Å to 3000 Å covered by titanium silicide or another metal silicide having a thickness of greater than 100 Å. The silicide layer provided on the polysilicon layer acts as a lower resistance conduction path in parallel with the polysilicon layer over the entire length of the gate electrode.
A typical implementation of a multilayer, silicide on polysilicon electrode is the so-called self-aligned silicide (“salicide”) structure, aspects of which are illustrated schematically in
FIGS. 1-6
. The illustrated MOS devices are formed on a P-type substrate
10
which includes, for example, thick field oxide regions to provide isolation from other, adjacent MOS devices. As is conventional, the device isolation structures may be formed by a local oxidation of silicon (LOCOS) process or one of the modified LOCOS processes. Often, however, device isolation is provided by a shallow trench structure formed by etching a trench into the substrate and refilling the trenches with a deposited insulator, such as an oxide provided by chemical vapor deposition (CVD). A gate oxide layer
12
is formed by thermal oxidation over the active device region between the device isolation structures and a polysilicon gate electrode
14
is formed on the gate oxide layer
12
. The polysilicon gate electrode
14
is formed by depositing a layer of undoped polysilicon over the substrate, typically using low pressure chemical vapor deposition (LPCVD), s implanting impurities into the polysilicon and annealing to activate the impurities and to render the polysilicon conductive. The polysilicon layer is patterned using conventional photolithography. Polysilicon wiring lines are typically formed elsewhere on the integrated circuit device at the same time and in the same maimer as gate electrode
14
is formed.
Doped source/drain regions
16
,
18
are formed on either side of the polysilicon gate electrode to define the channel region of the illustrated MOS field effect transistor. Often, a lightly doped drain (LDD) structure is used in small design rule MOS transistors of the type that are frequently used in modern memory and logic devices. LDD source/drain regions are typically formed in a two step process, beginning with a relatively low level ion implantation made self-aligned to polysilicon gate electrode
14
to form the structure illustrated in FIG.
1
. Subsequently, insulating sidewall spacer structures
20
(
FIG. 2
) are formed on either side of the gate electrode by first depositing a layer of CVD oxide over the
FIG. 1
structure and then anisotropically etching back the oxide layer to expose the substrate over the lightly doped source/drain regions
16
,
18
. Etching back the CVD oxide layer produces the spacer oxide structures
20
on either side of the polysilicon gate electrode
14
. After the spacer oxide regions
20
are provided on either side of the polysilicon gate electrode
14
, a second, heavier ion implantation is made into the source/drain regions
22
,
24
self-aligned to the spacer oxide regions
20
.
For smaller line widths, even highly doped polysilicon is sufficiently resistive to diminish the performance of MOS and other types of integrated circuits which include polysilicon electrodes or which otherwise incorporate polysilicon electrodes because the resistivity of the polysilicon reduces signal levels and produces longer RC time constants in the associated circuits. To reduce the resistance of conventional polysilicon gate electrodes, further processing of the
FIG. 2
device continues to convert the polysilicon gate electrode into a silicide structure using self-aligned silicide (salicide) techniques. Although a variety of different suicides are known to be acceptable, the silicide most commonly used at this time is titanium silicide, and that structure is described herein
Referring now to
FIG. 3
, the salicide structure is formed on the polysilicon electrodes and the source/drain regions within the substrate by first sputtering a layer
25
of titanium over the surface of the device to a thickness of, for example, 500 Å. This titanium layer
25
is converted into titanium silicide at the surface of the polysilicon gate electrodes and at the exposed portions of the substrate, including the source/drain regions
22
,
24
, in a two step annealing process. In the first process step, the device is subjected to a rapid thermal anneal (RTA) by heating the device to a temperature of up to about 700° C. for about thirty seconds. The first RTA process is followed by an etch to remove unreacted portions of the titanium layer, leaving behind the titanium silicide, and then the titanium silicide is further processed in a second RTA process to achieve a desired form of the titanium silicide layers. The first RTA step of the process converts the titanium layer into titanium silicide (nominally TiSi
2
) where the titanium layer is in contact with a silicon (crystalline or polycrystalline) surface during the anneal. A layer of titanium silicide
26
is formed over the polysilicon gate electrode
14
and titanium silicide regions
28
,
30
are formed over the source/drain regions
22
,
24
exposed during the silicidation process, as illustrated in FIG.
4
. Titanium silicide regions
28
,
30
over the source/drain regions
22
,
24
are often preferred, particularly for logic devices, because silicided source/drain regions provide lower sheet resistance within the source/drain regions and provide better contacts to the source/drain regions
22
,
24
than polysilicon. Silicided contacts on the source/drain regions are preferred so long as the amount of silicon consumed in the silicidation process does not alter the transistor performance or result in excessive junction leakage at the source/drain regions.
After the initial RTA step, the surface of the device is subjected to a wet etch consisting of H
2
O
2
and NH
4
OH diluted in water to remove unreacted titanium and a variety of undesired titanium compounds from the surface of the device and to expose the oxide regions
20
of the device, as illustrated in FIG.
5
. After the unreacted titanium is removed from the device, further processing is necessary to provide suitable silicide layers on the gate electrodes and over the source/drain regions. The titanium silicide formed in the first annealing step described above (RTA at about 700° C. for 30 sec.) is a relatively high resistivity metastable phase (known as the “C-49” phase) of titanium silicide on the silicon surfaces, that does not have as low of resistivity as is desirable. It is accordingly necessary to expose the device to a second annealing step at a temperature in excess of 800° C. for at least ten seconds in order to convert the higher resistivity C-49 phase of titanium silicide to the lower resistivity orthogonal phase (known as the “C-54” phase) of titanium silicide. The device is then subjected to further processing to complete fabrication.
A number of the processing steps necessary to the formation of salicide structures according to the above method are critical. If the temperature control is poor for the initial RTA step of converting the titanium in contact with silicon to titanium silicide, e.g., the temperature for the initial anneal is nea

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