Circuit fabrication method which optimizes source/drain...

Details Circuit fabrication method which optimizes source/drain... Circuit fabrication method which optimizes source/drain...

1999-01-04

2001-07-24

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

C438S682000, C438S649000, C438S487000

Reexamination Certificate

active

06265291

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to integrated circuit (IC) devices and processes of making IC devices. More particularly, the present invention relates to an IC which is optimized for small size and low source/drain contact resistance.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) include a multitude of transistors formed on a semiconductor substrate. Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally built on the top surface of a bulk substrate. The substrate is doped to form impurity diffusing layers (i.e. source and drain regions). Between the source and drain regions is a conductive layer which operates as a gate for the transistor. The gate controls current in a channel between the source and the drain regions.
To reduce series resistance associated with the source and drain regions, manufacturers use a process known as “silicidation.” Typically, silicidation is accomplished by depositing a refractory metal (e.g. Co, Ti, Ni) onto an exposed surface of source and drain regions in a semiconductor substrate. The atoms of silicon (Si) in the source and drain regions react with the atoms of the refractory metal, forming a silicide layer. The layer of silicide reduces the contact resistance at the silicide source/drain junction by helping break through the residual surface oxide so that good electrical contact can be made.
As MOSFETs are made smaller and smaller, however, the source and drain regions become more shallow and contact resistance associated with the source and drain regions increases. The source/drain contact resistance (i.e. silicide junction resistance) is very critical to transistor performance. High contact resistance degrades the transistor drive current and, thus, also degrades transistor speed and performance.
U.S. Pat. No. 5,258,637, issued Nov. 2, 1993, and U.S. Pat. No. 5,108,954, issued Apr. 28, 1992, both to Sandhu and Anjum, disclose a method of reducing contact resistance at silicide/active area interfaces. Sanhu and Anjum explain that during the elevated temperature anneal to form the silicide, the conductivity enhancing impurity (or dopant) tends to diffuse toward the silicide region. The void of dopants near the silicide increases the contact resistance between the silicide and active areas.
In the process disclosed by Sandhu and Anjum, germanium is implanted through the contact opening and into the active area of the wafer. As such, the germanium restricts diffusion of the conductivity enhancing impurity therethrough during the silicide anneal. While the germanium implant may reduce the contact resistance caused by a void of dopants near the silicide, the Sanhu and Anjum process does not optimize the contact resistance by maximizing the level of dopants proximate to the silicide.
The conventional method of silicidation makes it very difficult to locate the bottom of the silicide layer in the region of peak dopant concentration during transistor fabrication. The least contact resistance would be achieved by locating the bottom of the silicide layer in the peak dopant concentration. Physically, though, conventional methods cannot do this. The manufacturing process can be varied by random process variation, making precise placement of the silicide layer difficult. Further, the peak is usually located close to the surface of the silicon semiconductor layer. When silicidation occurs, the silicon is consumed, locating the bottom of the silicide layer deeper than the peak. As the amount of contact resistance resulting from fabrication depends on how close the bottom of the silicide formation is to the peak dopant concentration, the conventional fabrication process results in excessive contact resistance.
Thus, there is a need for a method to optimize MOSFET source/drain contact resistance in the fabrication process. Further, there is a need to reduce the contact resistance without implanting germanium at a precise location in the source/drain regions. Even further, there is a need for fabricating a transistor such that the bottom of the silicide always intersects with a high density of dopant.
SUMMARY OF THE INVENTION
One embodiment of the invention relates to a method of manufacturing an integrated circuit. The method includes implanting a first material in a layer of semiconductor, the first material creating a buried amorphous layer; implanting a second material in the layer of semiconductor and layer of amorphous semiconductor, the second material forming a profile region with a curved shape; depositing a layer of metal on the layer of semiconductor; exposing laser energy to the integrated circuit such that the amorphous semiconductor layer is melted and the profile region has a box-like shape; and forming a semiconductor/metal layer with the layer of semiconductor and the layer of metal, whereby the bottom of the semiconductor/metal layer is located in the profile region.
Another embodiment of the invention relates to a method of manufacturing an integrated circuit including amorphosizing a silicon structure, creating a buried amorphous silicon structure; implanting an ion in the silicon structure and amorphous silicon structure; depositing a layer of metal on the silicon structure; exposing laser energy to the integrated circuit such that the amorphous silicon structure is melted; and forming silicide with the silicon structure and layer of metal, the bottom of the silicide located in the amorphous silicon structure.
Another embodiment of the invention relates to a method of manufacturing an ultra-large scale integrated circuit including a plurality of transistors, each transistor having a layer of silicon with impurity diffusing layers and a layer of silicide adjacent each impurity diffusing layer, the contact resistance between the impurity diffusing layers and the corresponding layer of silicide being optimized. The method includes amorphosizing the layer of silicon, creating a buried amorphous silicon layer; implanting a dopant in the layer of silicon and amorphous silicon layer; depositing a layer of metal on the insulator structure; exposing laser energy to the integrated circuit such that the amorphous silicon layer is melted; and forming silicide with the insulator structure and layer of metal, the bottom of the silicide located in the amorphous silicon layer.


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“Ultra-Thin-Body Silicon-on Insulator MOSFET's for Terabit-Scale Integration” by Yu, et al., Department of Electrical Engineering & Computer Sc

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