Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-09-22
2001-09-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C430S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06295633
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates to a technique applied to designing of a circuit such as an LSI (Large Scale Integration) or a PCB (Printed Circuit Board).
It is a common practice to perform, after logical designing, floor planning in order to mount a result of the logical designing. While also it is a common practice to temporarily mount a result of logical designing to verify the same and feed back a result of the verification to the logical designing, also upon such temporary mounting, floor planning is performed.
A result of logical designing of a design object circuit is normally divided into a plurality of circuit parts of sizes which are easy to handle. The circuit parts are called sub circuits (or divided circuits). Then, in the floor planning, physical blocks having areas necessary to mount the sub circuits in a mounting region are determined first, and then the physical blocks determined corresponding to the sub circuits are arranged in the mounting region.
The present invention relates to an apparatus for and a method of executing such floor planning as described above and also to a computer-readable recording medium on which a floor planning program for realizing the apparatus and the method is recorded.
2) Description of the Related Art
Usually, floor planning is performed upon mounting of a circuit after logical designing or upon temporary mounting of a circuit for verifying a result of logical designing.
As described above, a result of logical designing of a design object circuit is normally divided into a plurality of sub circuits (divided circuits) of sizes which are easy to handle. Each sub circuit is composed of a plurality of circuit units (which may be hereinafter referred to as minimum circuit units). Where the design object circuit is an LSI, the minimum circuit unit is a cell.
In an ordinary floor planning apparatus, the shapes of physical blocks onto which sub circuits are to be mounted in a mounting region are limited to rectangles, and the area (size) of each physical block is either designated by an operator (a user or a designer) or automatically produced based on a duty (=circuit area/region area) and an aspect ratio designated by an operator, and the theoretical shape of the physical block is displayed. Here, for the circuit area, a sum total of the areas of a plurality of minimum circuit units (for example, leaf cells) which compose each sub circuit.
Thereafter, in the ordinary floor planning apparatus, the physical blocks (rectangles) whose shapes/areas are set for the individual sub circuits are arranged as they are in the mounting region to determine the arrangement positions of them. In this instance, the physical blocks are usually arranged such that they do not overlap with any other physical block. For example, where ten physical blocks B
1
to B
10
are set as shown in
FIG. 8
, they are arranged, for example, in such a manner as shown in
FIG. 9
in a mounting region.
However, when the areas of the physical blocks are determined as described above, if an operator designates the areas of the physical blocks one by one for the sub circuits, not only is much time required for the floor planning and a much burden is imposed on the operator, but also the floor planning is inefficient. Thus, it is demanded to automate the determination of the areas of physical blocks.
Further, where the ordinary technique wherein the areas of physical blocks are automatically produced and determined as described above is employed, only the shapes/areas are automatically produced by designating the duties and the aspect ratios determined taking the areas of minimum circuit units into consideration. The area of a physical block should be determined roughly in accordance with a number of parts (for example, basic cells) of minimum circuit units of the physical block. The area, however, is influenced, in the case of an LSI, not only by basic cells, but also by wiring regions of the sub circuit (the number of areas in which the wiring region is included) pins, networks, fan-outs and so forth. Accordingly, the area of a physical block determined based on a duty determined taking only the areas of basic cells of leaf cells (minimum circuit units) into consideration is not considered to sufficiently match an actual sub circuit, but matters in regard to the accuracy and may possibly give rise to some trouble when mounting designing is performed so as to arrange circuit parts in a high density.
Further, since physical blocks are usually limited to rectangles and arranged such that they do not overlap with any other physical block as described above, if physical blocks B
1
to B
10
of various shapes/areas are arranged as seen in
FIG. 9
, then it is impossible to fully fill up gaps (refer to slanting line regions in
FIG. 9
) among the physical blocks B
1
to B
10
, and it cannot be avoided that a plurality of non-used regions appear in the mounting region, which makes it difficult to efficiently use the mounting region. The presence of such non-used regions increases the distances between the physical blocks and consequently increases the lengths of wiring lines between the physical blocks, and this has an influence upon delays of signals and besides gives rise to such a subject that it disturbs high density integration of circuits. Further, the non-used regions appear in most cases as elongated rectangles, and physical blocks which can be arranged in the non-used regions are limited very much in terms of the size and the shape. Consequently, even if it is tried to arrange physical blocks in the non-used regions, those physical blocks which can be arranged are limited.
It seems possible to use, without limiting the shapes of physical blocks to rectangles, various shapes (polygons). In this instance, such subjects as described above are not invited. However, in order to designate a shape other than a rectangle, it becomes necessary to support plotting of a polygon, and this makes operation by an operator very complicated.
For example, if it is tried to set the shape of a physical block to a shape other than a rectangle, then an operator must perform such operation as to first perform an operation for plotting a polygon and then perform, since a duty is fed back as a result of the operation, re-plotting taking the duty into consideration.
Accordingly, from the reason that, upon production of a shape of a physical block from the area of the physical block, the shape can be determined very simply, the shapes to be produced by an ordinary floor planning apparatus are in most cases limited to rectangles.
However, in order to eliminate the problem of signal delays with certainty while an increase in density of circuitry in recent years is satisfied, it is intensely demanded to make it possible to produce a physical block of a shape other than a rectangle using a very simple technique.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a floor planning apparatus and a floor planning method as well as a computer-readable recording medium having a floor planning program recorded thereon by which physical blocks having areas sufficiently matching with actual sub circuits can be produced automatically and also a physical block of a shape other than a rectangle can be produced using a very simple technique to allow physical blocks to be arranged efficiently in a mounting region and eliminate the problem of signal delays with certainty while satisfying an increase in density of circuitry.
In order to attain the objects described above, according to an aspect of the present invention, there is provided a floor planning apparatus which determines, in order to mount a design object circuit, for each of sub circuits obtained by dividing the design object circuit, a physical block having an area necessary to mount the sub circuit in a mounting region and arranges the physical blocks in the mounting region, comprising a circuit unit recognition section for recognizing circuit units which compose each of the su
Fujitsu Limited
Smith Matthew
Speight Jibreel
Staas & Halsey , LLP
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