Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-03-31
2001-03-20
Wright, Norman M. (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S033000, C714S741000
Reexamination Certificate
active
06205559
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for diagnosing and estimating a failure occurrence position in a semiconductor integrated circuit device and a failure diagnosing apparatus for the same. More specifically, the present invention relates to a method for diagnosing and estimating a failure occurrence position in a semiconductor integrated circuit device by using an IDDQ test (power source current quiescent test) result of the semiconductor integrated circuit device and a failure diagnosing apparatus for the same.
2. Description of the Related Art
A failure diagnosing apparatus for a semiconductor integrated circuit may be used to specify a failure occurrence position occurred in the semiconductor integrated circuit device, and to confirm a reason of this failure.
For instance, such a failure diagnosing apparatus is described in Japanese Laid Open Patent Disclosure (JP-A-Heisei 4-55776). In the failure diagnosing apparatus, a failure is assumed to occur in a semiconductor integrated circuit device, and an expected value is calculated from a logical simulation result of the semiconductor integrated circuit device. Then, the calculated expected value is compared with a value actually measured by a general-purpose tester such that a failure occurrence position is specified.
However, there is the following problem in the above-described conventional failure diagnosing apparatus for the integrated circuit. That is, when the occurrence of a failure is assumed, since the logic simulation is executed with respect to all of the possible failure factors, the logical simulation for a long time would be necessarily required. Accordingly, the failure diagnosing time would be prolonged.
In addition, in Japanese Laid Open Patent Disclosure (JP-A-Showa 61-241672), the technique is described, in which a test apparatus is composed of simulation means, a pattern generator for converting a test pattern into an electric signal, a test head for applying the electric signal to an IC, comparing means for comparing the output from the IC with an expected value outputted from the simulation means, and fault analysis means for referring to a fault simulation data to determine a fault position when both are not coincident.
In Japanese Laid Open Patent Disclosure (JP-A-Showa 63-305265), the technique is described in which a fault analysis apparatus for a semiconductor integrated circuit is composed of a logic simulator for inputting an input pattern data and a circuit diagram data to output a simulation result, a tester for inputting an input pattern which is edited based on the simulation result, and an output expectation pattern to output a fault output pin number and a test period data, a fault simulator for inputting the input pattern data and the circuit diagram to output a simulation period, a detected fault data and a list of fault detection percentages, and a fault analysis unit for inputting the fault output pin number, a test period data, the simulation period, the detected fault data and the circuit diagram data to output a fault position data.
In Japanese Laid Open Patent Disclosure (JP-A-Heisei 6-120314), the a semiconductor integrated circuit is described to which a test is easily performed. In this reference, a group of test cells is provided on a semiconductor substrate in a matrix manner of m rows and n columns.
In Japanese Laid Open Patent Disclosure (JP-A-Heisei 7-77562), a short circuit failure diagnosing data generating method is described in which a short circuit failure model circuit is inserted between an LSI in which a boundary scanning function is incorporated and a cluster to make a short circuit failure diagnosis possible. The short circuit failure model circuit replaces the short circuit failure of input signals from the cluster into a degenerate failure of signals in the model circuit.
In Japanese Laid Open Patent Disclosure (JP-A-Heisei 1-156680), a fault diagnosing method is described in which a means is provided to calculate a fault detection probability from a logic simulation result by setting an observation probability to 1 only for an external output terminal in which a fault is detected, and setting the observation probability to 0 for other external output terminals, based on fault detection information from an LSI tester, and in which a fault cause is specified by use of the fault detection probability.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above-described conventional problems. Therefore, an object of the present invention is to provide a method for diagnosing and estimating a failure occurrence position in a semiconductor device with a short time period and a failure diagnosing apparatus for the same.
Another object of the present invention is to provide a method for correctly estimating a failure occurrence position in a semiconductor device such that the reliability of a product can be increased, and a failure diagnosing apparatus for the same.
In order to achieve an aspect of the present invention, a method of diagnosing a test circuit device, includes the steps of:
simulating an operation of a test circuit device using a set of test vectors to produce a simulation result;
testing the test circuit device using the set of test vectors to produce a test result;
defining a first set of combinations of circuit elements based on a circuit data of the test circuit device, the test circuit device being composed of the circuit elements;
estimating a final set of failure candidates from the first set of combinations based on the simulation result and the test result for each of the test vectors; and
outputting the final set of failure candidates.
In the simulating step, the operation of the test circuit device in a gate level may be simulated based on the circuit data and the test vectors to produce gate level simulation result, and the gate level simulation result may be converted into the simulation result in a transistor level.
Also, in the defining step, the first set of combinations of every two of the circuit elements may be defined based on the circuit data of the test circuit device, and combinations of the circuit elements may be selected based on a layout data of the test circuit device such that any failure does not occur, to define a second set of the selected combinations. Thus, the second set is removed from the first set to redefine the first set of combinations.
The estimating step may include:
(a) determining a third set of combinations of the circuit elements in which a failure does not occur, based on the simulation result for a specific test vector;
(b) removing the third set of combinations from the first set of combinations to redefine the first set of combinations; and
(c) repeating the steps (a) and (b) while changing the specific test vector over the test vectors.
Alternatively, the estimating step may include:
(d) determining a third set of combinations of the circuit elements in which a failure does not occur, based on the simulation result for a specific test vector;
(e) removing the third set of combinations from the first set of combinations to redefine the first set of combinations; and
(f) repeating the steps (d) and (e) while changing the specific test vector over ones of the test vectors other than a predetermined range of test vectors.
Also, the estimating step may include:
(g) initializing values for the combinations of the first set;
(h) determining a third set of combinations of the circuit elements in which a failure does not occur, based on the simulation result for a specific test vector;
(i) incrementing the values for ones of the combinations of the first set corresponding to the combinations of the third set; and
(j) repeating the steps (h) and (i) while changing the specific test vector the test vectors.
Instead, the estimating step may include:
(k) initializing values for the combinations of the first set;
(l) determining a third set of combinations of the circuit elements in which a failure does not occur, based
Foley & Lardner
NEC Corporation
Wright Norman M.
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