Silicon-on-insulator non-volatile random access memory device

Details Silicon-on-insulator non-volatile random access memory device Silicon-on-insulator non-volatile random access memory device

1999-01-07

2001-06-26

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S214000, C257S315000, C257S316000, C257S321000, C257S322000

Reexamination Certificate

active

06252275

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to nonvolatile memory devices and, more specifically, to integrated circuits used for Non-Volatile Random Access Memory (NVRAM) devices.
BACKGROUND OF THE INVENTION
Non-volatile memory devices are electrically programmable and erasable to store charge in a location within the device and to retain that charge when power to the device is shut off. An array of non-volatile devices that allows individual locations to be read with random access is called a Non-Volatile Random Access Memory (NVRAM).
The key to operation of the NVRAM is an individual semiconductor device whose conduction state can be altered by the presence or absence of charge in an insulating layer, or in a conductive layer imbedded in an insulating layer, in close proximity to the conduction channel of a MOSFET (Metal-Oxide-Silicon Field Effect Transistor). The non-volatile character of the storage depends on the ability of the device to retain that charge for long periods of time even when power is not applied to the device. One device type stores charge in the insulating layer of the MOSFET, typically at the interface of a nitride-oxide dual layer deposited on a silicon substrate forming the channel of a MOSFET. This device is commonly called an MNOS (Metal-Nitride-Oxide-Silicon) device.
Another embodiment of an NVRAM device uses the charge stored in a polysilicon layer that is electrically isolated from the conduction channel in the silicon by a thin layer of insulating material, typically silicon dioxide. This device, described in U.S. Pat. No. 4,203,158 issued to Froman-Bentchkowsy et al. and assigned to the Intel Corporation of Santa Clara, California, is known as a Floating Anode MOS (FAMOS) or Insulated Gate Field Effect Transistor (IGFET).
Both the IGFET and the MNOS work by injecting or tunneling charge generated in the silicon substrate or diffusions by application of high voltages to the silicon terminals. The high electrical field across the device injects or tunnels charge into or across the insulating layer into a storage region. In the MNOS device, the silicon nitride-silicon oxide interface stores the charge. In the IGFET, the floating polysilicon gate stores the charge.
The ability of the devices to change their state through a large number of read-write-erase cycles is an important consideration in the use of NVRAM devices. That ability is called “cyclability.” NVRAM devices must be able to cycle in excess of a million times without any degradation in performance or difficulty in discrimination between a “1”or a “0”. In practice, cyclability depends on the device type and the process steps used in the device fabrication. Eventually, however, the erase-write operations that change the device charge state may degrade the cyclability of individual devices.
Referring now to
FIG. 1
, there is shown an IGFET device
19
of the prior art. For writing and erasing in IGFET device
19
, diffusion regions
11
and
11
′ or control gate
12
inject carriers into the polysilicon floating gate
14
. The diffusion regions
11
and
11
′ typically do the writing and the control gate
12
does the erasing. An oxide layer
16
(which may comprise a number of oxide layers, depending on the fabrication technique) separates the floating gate
14
from the control gate
12
and the single crystal silicon substrate
10
.
After the charge has been written or erased, the diffusion regions
11
,
11
′ may function as a sensing element. By applying a first voltage to one diffusion region
11
and measuring the ability of the current to flow to the other diffusion region
11
′ biased at a second, lower voltage, the charge state of the floating gate
14
may be determined.
NVRAM devices commonly use two methods of charge injection and removal. In the first method, hot carriers are injected by a source of hot carriers generated in the channel
17
between the diffusion regions
11
and
11
′ or from biasing the diffusion regions
11
and
11
′ to be close to or in avalanche breakdown. In the other method of injecting charge, Fowler-Nordheim (FN) tunneling transports charge from the silicon substrate
10
. Achievement of avalanche breakdown or hot electron injection requires a single crystal silicon layer. Generally, injection by avalanche breakdown or hot carrier injection uses a lower voltage than FN tunneling, so the first method is preferred.
Referring now to
FIG. 2
, there is shown an IGFET device
19
′ that uses FN tunneling. Floating gate
14
′ of device
19
′ has an injector tab
15
over diffusion region
11
. The injector tab
15
reduces the oxide thickness between diffusion region
11
and floating gate
14
, thus reducing the voltage required for FN tunneling.
When the single crystal silicon substrate
10
is the source or sink for the injected carriers by either avalanche injection or FN tunneling, the silicon interface that forms the active electrical channel
17
for the FET is subjected to high fields. The high fields may lead to the formation of interface states and trapped charge in the oxide. Thus, during each write cycle, some fraction of the generated charge may become permanently trapped in the gate oxide and will not erase. As this unwanted charge accumulates in the oxide, the threshold voltage of a cycled device gradually approaches a value that cannot distinguish between a device in a “1” state or a “0” state, and the device ceases to operate correctly. This excess of accumulated charge is not reversible, and thus the cyclability window—the number of times the device can be written and erased—is reduced.
The high electric fields required to inject carriers into the floating gate also pose problems because the injecting diffusion regions
11
,
11
′ are also the source and drain of the FET that is the sensing element of the device. The high fields necessary for injection degrade the ability of the device to sense the state of the floating gate
14
as it is cycled many times.
A number of solutions have been implemented in NVRAM circuits to address these problems. One solution uses higher voltages to compensate for the trapped charge that gives a false reading for gate charge. Another solution physically removes the injection point away from the sensing element so that the impact of the charge generated in the write-erase cycle has no effect on the channel of the sensing element. Many of these solutions take up too much space, and are thus not widely practiced in the industry.
Therefore, there is still a need in the industry for an NVRAM device that lowers the voltages at which charge can be written and erased, and that improves the cyclability of the device.
SUMMARY OF THE INVENTION
To meet this and other needs, and in view of its purposes, the present invention provides an NVRAM structure comprising an injector element in a single crystal silicon substrate; an insulator layer over the substrate; a silicon-on-insulator (SOI) layer over the insulator layer; and a sensing element in the SOI layer overlying the injector element. The NVRAM structure may further comprise a gate above the SOI layer, a floating gate in the insulator layer, or both. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.


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