Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1997-12-31
2001-01-09
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S721000, C327S176000, C327S264000, C327S291000, C365S189090, C365S201000
Reexamination Certificate
active
06173424
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to pulse generators, and more particularly, to a pulse generator for generating pulses which vary between at least two programmable voltage levels.
BACKGROUND OF THE INVENTION
Semiconductor devices such as memory devices are tested during manufacture by applying pulses to a terminal of a selected memory device while data is being written to or read from the memory device. Ideally, the operation of the memory device during such a test will not be affected by the pulses. The pulses are typically provided from a pulse generator. It is often desirable to program the voltage levels of the pulses with a programmable pulse generator. It is also desirable that the pulses have relatively high voltage levels with a fast rise time and a fast fall time.
One conventional method of generating pulses at programmable voltage levels is to generate a standard logic level pulse from a conventional logic device such as a CMOS gate, a Field Programmable Gate Array (FPGA), or an Application-Specific Integrated Circuit (ASIC). The standard logic level pulse is then converted to a programmable level by an additional circuit such as a pin driver device. Pin driver devices are general purpose devices used in a wide range of applications. However, pin driver devices generally do not have the capability to generate relatively high voltage level pulses which have a fast rise time and a fast fall time.
Programmable pulses may also be generated by a conventional pulse generator
10
shown in FIG.
1
. The pulse generator
10
includes three voltage sources
12
,
14
, and
16
. Each of the voltage sources
12
,
14
, and
16
has an output coupled to an input of a respective one of three electromechanical relays
18
,
20
, and
22
. Each of the electromechanical relays
18
,
20
, and
22
has an output coupled to an output terminal
24
, and it receives a respective control signal from a system logic circuit
26
. The system logic circuit
26
generates the control signals to render each of the electromechanical relays
18
,
20
, and
22
conductive in a sequence to couple the outputs of the voltage sources
12
,
14
, and
16
to the output terminal
24
in a sequence to generate voltage pulses. The voltage pulses may be applied to a memory device
28
coupled to the output terminal
24
.
The electromechanical relays
18
,
20
, and
22
have a slow reaction time and, as a result, there is a long delay between a change in one of the control signals and a change in the conductive state of the electromechanical relay which receives the control signal. The slow reaction time of the electromechanical relays
18
,
20
, and
22
slows the operation of the pulse generator
10
with respect to the speed of operation of the memory device under test. The slow operation of the pulse generator
10
adds significant overhead cost to a test of a memory device.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved pulse generator is provided that is structured to generate pulses to be provided to an input terminal of a semiconductor device. The pulse generator includes several electronic switches. Each electronic switch has a control terminal, an input terminal coupled to one of several differentiated voltage sources, and an output terminal coupled to the input terminal of the semiconductor device. The pulse generator also includes a control logic circuit having several outputs, each output being coupled to the control terminal of one of the electronic switches. The control logic circuit is structured to render selected electronic switches conductive in a sequence to couple selected ones of the voltage sources to the input terminal of the semiconductor device in a sequence. Each electronic switch may be a pass gate, and one of the voltage sources may be a ground voltage reference. In addition, the remaining voltage sources may be programmable voltage sources each having a voltage control signal input coupled to receive a voltage control signal from the control logic circuit.
In another embodiment, a method is provided for testing a semiconductor device having an input terminal. Each of several electronic switches are coupled between one of several differentiated voltage sources and the input terminal of the semiconductor device. Each of the electronic switches is controlled to be rendered conductive or nonconductive in a sequence to couple selected ones of the voltage sources to the input terminal of the semiconductor device in a sequence.
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patent: 4415861 (1983-11-01), Palmquist et al.
patent: 4766328 (1988-08-01), Yang
patent: 5297151 (1994-03-01), Gruetzner et al.
patent: 5317532 (1994-05-01), Ochii
patent: 5376849 (1994-12-01), Dickol et al.
patent: 5390192 (1995-02-01), Fujieda
patent: 5801566 (1998-09-01), Tanaka
patent: 5878055 (1999-03-01), Allen
patent: 5886428 (1999-03-01), Feiler et al.
Lindsay R. Brent
Voshell Thomas W.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Moise Emmanuel L.
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