Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-03-23
2001-03-13
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S185200
Reexamination Certificate
active
06201742
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a circuit that prevents illegal transformation of data in a non-volatile memory and method for the same. More specifically, this invention relates to a technology that makes it possible to prevent a malfunction in data reading caused due to charge gain or charge loss to a floating gate constituting a cell in an electrically-rewritable non-volatile memory.
BACKGROUND OF THE INVENTION
An electrically-rewritable non-volatile memory can store and maintain data stored therein for more than ten years. Further, it is possible to electrically rewrite the data or delete the data. Therefore, the electrically-rewritable non-volatile memory has become indispensable as an important component of electronic equipment used in communications and/or data processing.
The reliability of data stored in the electrically-rewritable non-volatile memory is high. Further, this high reliability can be maintained for a long period of time even if no special processing is performed. Because of such a high reliability, however, if an illegal transformation of data transformation takes place, a system or the like that uses the electrically-rewritable non-volatile memory is seriously affected. In order to prevent the damage of the system, it is necessary to maintain the high reliability of the electrically-rewritable non-volatile memory for a long period of time.
FIG. 14
shows a general configuration of an example of a conventional electrically-rewritable non-volatile memory. As shown in
FIG. 14
, generally a memory call used in a non-volatile memory has the configuration in which an electrically-insulated floating gate
102
is provided in a MOS transistor structure between a p-type silicon substrate
103
and a control gate
101
. Accordingly, when electrons enter the floating gate
102
, the electrons can not escape because the floating gate
102
is electrically insulated. When a voltage is loaded to an n-type drain
105
and an n-type source
104
and further a voltage is loaded to the control gate
101
, then a current Ids starts flowing from the n-type drain
105
to the n-type source
104
. The gate voltage when this current Ids starts flowing is termed as the threshold voltage Vth.
FIG. 15A
explains the operation of the electrically-rewritable non-volatile memory shown in
FIG. 14
when writing the data, and
FIG. 15B
explains the operation when deleting the data. When writing the data, as shown in
FIG. 15A
, a high voltage of 12 V is loaded to the control gate
101
, and a voltage of 0 V and a voltage of 6 V are loaded to the source
104
and the drain
105
respectively. When such voltages are loaded, the current Ids starts flowing between the drain
105
and the source
104
. However, the electric field near the drain
105
between the drain and source becomes stronger so that electrons are accelerated. As a result, the so-called hot electrons are generated, and some of the hot electrons pass through an energy barrier of an oxide film on the floating gate
102
and enter the floating gate
102
. Because of this phenomenon, electrons are injected into the floating gate
102
so that the threshold voltage Vth of the memory cell rises.
When writing the data, as shown in
FIG. 15B
, a voltage of 0 V is loaded to the control gate
101
and a voltage of 12 V loaded to the source
104
, and the drain
105
kept open. In this case, a high electric field is generated in the portion between the source
104
and floating gate
102
, and because of a physical effect called the Fowler-Nordheim tunnel, the electrons from the floating gate escape to the source
104
. Because of this escape of electrons from the floating gate
101
, the threshold voltage in the memory cell drops.
FIG.
16
A and
FIG. 16B
explain an operation for reading out data from the memory cell which data has been written in or deleted from due to the data write/delete operation shown in FIG.
15
A and FIG.
15
B. When data is to be read out, a voltage of 5 V is loaded to the control gate
101
, and a voltage of 2 V is loaded to the drain
105
and a voltage of 0 V is loaded to the source
104
.
FIG. 16A
explains the operation of reading out data from the memory cell which is in a data-written state (data-written state means that some data has already been written in the memory cell). In the case shown in
FIG. 16A
, electrons are injected into the floating gate
102
, so that a voltage loaded to the control gate
101
is canceled and the current Ids does not flow.
FIG. 16B
explains the operation of reading out data from the memory cell which is in a data-deleted state (data-deleted state means that the data has already been deleted from the memory cell). In the case shown in
FIG. 16B
, there are no electrons in the floating gate
102
, so that a voltage loaded to the control gate
101
functions as a gate voltage and the current Ids flows. Thus, the current Ids does not flow in a memory cell that is in the data-written state because electrons are injected into the floating gate
102
. When it is detected that no current flows, information “0” is readout. On the other hand, the current Ids flows in a memory cell that is in the data-deleted state because electrons are not injected into the floating gate
102
. When it is detected that current Ids flows, information “1” is read.
As described above, by loading a voltage of 5 V to the control gate, a state of the memory cell is determined by checking whether the current Ids flows between the source and drain.
FIG. 17
shows a relation between a magnitude of the current between the drain and the source in a reference cell based on the conventional technology and a magnitude of the current between the drain and the source in a memory cell which is in data-written state or state-deleted state. In
FIG. 17
, the horizontal axis represents a voltage Vgs between the gate and the source and the vertical axis represents the current Ids between the source and the drain.
As can be confirmed from
FIG. 17
, when a voltage Vread for reading out data is loaded to the control gate
101
, the current Ids flows between the source
104
and the drain
105
as explained above. Whether the current Ids flows or not can be determined by checking whether the current Ids when the voltage is Vread is greater than a threshold of the reference current Iref
1
. Precisely, when the current Ids is greater than the reference current Iref
1
, it is considered that the current Ids is detected and in this case information “1” is output. On the other hand, when the current Ids is equal to or less than the reference current Iref
1
, it is considered that the current Ids is not detected and in this case information “0” is output. When the written state of the memory cell is normal, the current when the voltage is Vread is assumed to be Ids
0
. When the data deleted state of the memory cell is normal, the current when the voltage is Vread is assumed to be Ids
1
. The magnitude of the reference current Iref
1
is set in such a manner that it is less than the magnitude of the current Isd
1
and greater than the magnitude of the current Ids
0
.
FIG. 18
shows an example of a conventional circuit which reads data from a non-volatile memory when the current Ids is detected. As shown in
FIG. 18
, a sense-amplifier SA compares a current Icell as the current Ids from a memory cell in a memory cell array with a reference current Iref
1
from a reference current cell. By outputting information “1” or “0” to a not shown output buffer based on this comparison, data is read out from the memory cell array.
In the conventional type of non-volatile memory as described above, when electrons are injected into or discharged from the floating gate
102
, it is assumed that this state is preserved permanently.
Recently, in association with the tendency for a higher degree of integration and the need for reduction of power consumption in a memory, the total amount of electric charge which can be accumulated in the floating gate
102
has reduced. Because the total amount of electric c
Asakawa Masashi
Hirai Tendo
Kousaki Yasuo
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fears Terrell W.
Fujitsu Limited
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