Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-08-26
2001-09-04
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S166000, C438S477000, C438S487000, C438S676000
Reexamination Certificate
active
06284577
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MIS (metal-insulator-semiconductor) semiconductor device such as a MOS field-effect transistor and to a manufacturing method therefor. The MIS semiconductor device according to the present invention is used in various semiconductor integrated circuits.
2. Description of the Related Art
With the size reduction in design rules of MIS semiconductor devices, a strong electric field between the drain and the channel now causes a hot carrier injection phenomenon. Degradations in characteristics due to the size reduction in design rules (i.e., shortening of the channel) are generally called short channel effects. To suppress the short channel effects, as shown in
FIG. 4
, a MIS field effect transistor having lightly doped impurity regions (lightly doped drain)
406
and
407
has been developed.
In this type of device, the LDDs
406
and
407
having an impurity concentration lower than a source
404
and a drain
405
are provided between the source
404
and -a channel forming region and between the drain
405
and the channel forming region. Having an effect of reducing the electric field, the LDDs
406
and
407
can suppress generation of hot carriers.
Conventionally, the LDDs
406
and
407
shown in
FIG. 4
are formed in the following manner. After a gate electrode
401
is formed, lightly doped impurity regions are formed by doping. Then, side walls
402
are formed with an insulating material such as silicon oxide, and the source and drain
404
and
405
are formed by conducting doping in a self-aligned manner using the side walls
402
as a mask.
However, since the gate electrode
401
does not extends over the LDDs
406
and
407
, the further channel reduction has caused a phenomenon in which hot carriers are trapped in portions of a gate insulating film
403
over the LDDs
406
and
407
. The trapping of hot carriers, particularly hot electrons, reverses the conductivity type of the LDDs
406
and
407
, to unavoidably causes such short channel effects as a threshold voltage variation, an increase of the subthreshold coefficient, and a reduction of the punch-through breakdown voltage.
To solve the above problem, the overlap LDD (GOLD) structure has been proposed in which the LDDs are also covered with the gate electrode. By employing this structure, there can be avoided the above-mentioned degradation in characteristics which would otherwise be caused by hot carriers trapped in the gate electrode over the LDDs.
As the MIS field-effect transistors having the GOLD structure, there was reported an IT-LDD structure (T.Y. Huang: IEDM Tech. Digest
742
(1986)). The IT-LDD structure means a LDD structure having an inverse-T gate electrode.
FIGS. 3A
to
3
E schematically show a manufacturing method of such a transistor.
After a field insulating film
302
and a gate insulating film
303
are formed on a semiconductor substrate
301
, a conductive coating
304
of, for instance, polycrystalline silicon is formed. (
FIG. 3A
)
A gate electrode
306
is then formed by etching the conductive coating
304
to a proper extent. Care should be taken not to etch the conductive coating
304
completely; that is, only portions
305
indicated by dashed lines should be etched to leave portions having a proper thickness (100 to 1,000 Å) around the gate electrode
304
, to thereby form a thin conductive coating
307
. Therefore, this etching step is very difficult.
LDDs
308
and
309
are formed by through-doping that is performed through the thin conductive coating
307
and the gate insulating film
303
. (
FIG. 3B
)
A coating
310
is then formed on the entire surface with such a material as silicon oxide. (
FIG. 3C
)
Subsequently, side walls
312
are formed by anisotropically etching the coating
310
in the same manner as in the case of producing the conventional LDD structure. The thin conductive coating
307
is also etched in this etching step. A source
313
and a drain
314
are formed by conducting doping in a self-aligned manner using the side walls
312
as a mask. (
FIG. 3D
)
Thereafter, an interlayer insulating film
315
, a source electrode/wiring
316
, and a drain electrode/wiring
317
are formed to complete a MIS field-effect transistor. (
FIG. 3E
)
The resulting structure is called IT-LDD because the gate electrode portion assumes an inverse-T as is apparent from the figures. In the IT-LDD structure, in which the thinner portions of the gate electrode exist over the LDDs, the carrier density in the LDD surfaces can be controlled to a certain extent from the gate electrode. As a result, even if the impurity concentration of the LDDs is lowered, there can be reduced the possibility of a reduction of the mutual conductance due to a series resistance of the LDDs or variations of the device characteristics due to hot carriers injected into the portions of the insulating film over the LDDs.
These advantages are not specific to the IT-LDD structure, but common to all kinds of GOLD structures. Capable of lowering the impurity concentration of the LDDs, the GOLD structure has a large effect of reducing the electric field strength. Further, since the LDDs can be made shallow, the GOLD structure can suppress the short channel effects and the punch-through.
There are no effective GOLD structure manufacturing methods other than the method of the IT-LDD structure. Although the IT-LDD structure have many advantages described above, it is very difficult to produce it. In particular, it is very difficult to control the etching of the conductive coating
307
(see FIG.
3
B). If there occurs a variation of the thickness of the thin conductive coating
307
among substrates or within a substrate, the impurity concentration of the source and drain varies, resulting in variations of the transistor characteristics.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problems in the art, and has an object of presenting a GOLD structure which can be produced more easily.
According to the present invention, a manufacturing method of a MIS semiconductor device comprises the steps of:
(1) forming a gate insulating film on a surface of a semiconductor;
(2) forming a gate electrode central portion;
(3) forming a lightly doped impurity region (LDD) in the semiconductor in a self-aligned manner using the gate electrode central portion as a mask;
(4) forming a conductive coating mainly made of silicon;
(5) forming a side wall spacer on a side face of the gate electrode central portion by anisotropically or semi-anisotropically etching the conductive coating in an atmosphere including a halogen fluoride; and
(6) forming a source or a drain in a self-aligned manner using the side wall as a mask.
The MIS semiconductor device produced by the above method is characterized by:
the gate electrode central portion formed on the gate insulating film;
the gate electrode side portion mainly made of silicon and formed in close contact with the side face of the gate electrode central portion; and
the LDD formed in the semiconductor under the gate electrode side portion between the drain (or source) and the channel forming region.
The MIS semiconductor device is further characterized in that a single insulating film mainly made of silicon oxide is formed on the drain, source, channel forming region, and LDD.
In the semiconductor device manufacturing method according to the present invention, the side wall is formed with a conductive material mainly made of silicon (i.e., formed with silicon having purity of more than 95%). That is, a GOLD structure is obtained by making the side wall a part of the gate electrode. To obtain such a structure, after a conductive coating mainly made of silicon is so formed as to cover a portion to become the gate electrode central portion, anisotropic or semi-anisotropic etching is performed in an atmosphere including a halogen fluoride. A halogen fluoride is represented by a chemical formula XF
n
where X is halogen excluding fluorine and n is an integer.
Suzawa Hideomi
Takemura Yasuhiko
Yamazaki Shunpei
Costellia Jeffrey L.
Lebentritt Michael
Nixon & Peabody LLP
Semiconductor Energy Laboratory Co,. Ltd.
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