Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-18
2001-04-10
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S349000, C257S350000, C257S354000
Reexamination Certificate
active
06215155
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor device configurations and manufacturing processes. In particular, the invention relates to a silicon-on-insulator (SOI) configuration and manufacturing process which is compatible with existing bulk complementary metal oxide semiconductor (CMOS) device architectures.
BACKGROUND OF THE INVENTION
Complementary metal oxide semiconductor (CMOS) devices that are produced in mass quantities are referred to as “bulk” CMOS, because they include a semiconductive bulk substrate on which active or passive circuit elements are disposed. Recently, silicon-on-insulator (also referred to as silicon-oxide-insulator) SOI CMOS devices have been introduced which consume less power than do bulk CMOS devices. SOI devices are characterized by a thin layer of insulative material (the so-called buried oxide layer, or “SOI”) that is sandwiched between a bulk substrate and the circuit elements of the device. Typically, no other layers of material are interposed between the SOI and the bulk substrate. In an SOI CMOS device, the circuit elements above the SOI are established by regions of a field oxide semiconductive layer which are doped as appropriate with N-type or P-type conductivity dopants. For example, for an N channel transistor, the field oxide layer will include a gate element disposed over a body region having a P-type dopant, with the body region being disposed between a source region and a drain region, each of which are doped with an N-type dopant. These devices provide an important advantage in many applications such as battery-powered mobile telephones and battery-powered laptop computers. Also, SOI CMOS devices advantageously operate at higher speeds than do bulk CMOS devices. SOI CMOS architecture eliminates inherent parasitic circuit elements in bulk CMOS due to junction capacitances between adjacent components. Also, CMOS circuits are very fast, due to the fact that the bulk capacitance is very small. SOI CMOS is also immune to latchup. Other problems surrounding the technology include the SOI floating-body effect. This particular problem has been addressed by others, by example, in a paper entitled “Suppression of the SOI Floating-body Effects by Linked-Body Device Structure,” by W. Chen, et. al., 1996 Symposium on VLSI Technology Digest of Technical Papers.
One of the obstacles facing the increased use of SOI CMOS architecture is the fact that there is an enormous economic design investment in modem VLSI integrated circuit (IC) products. Typically, standard SOI does not behave the same way as bulk CMOS because of the dielectric isolation, and bulk CMOS designs are thus generally not compatible with, or readily transferable to an SOI architecture. Product groups must decide whether to re-design circuits for SOI CMOS, even when the circuit functions adequately using bulk CMOS, especially since the fabrication facilities will not try to run any new technology without a baseline. Although the prior art teaches combination of bulk CMOS and SOI CMOS architecture, by example Chen et.al. teaches locating wells above the buried oxide layer, the prior art does not teach any layout compatibility between the two architectures nor does it teach placing wells below the buried oxide layer. Thus, a need is seen to exist to provide a SOI configuration which is compatible with current bulk CMOS architecture. Using a bulk CMOS database, it would then be possible to create products rapidly for SOI fabrication and technologies.
Accordingly, it is a primary object of the present invention to provide a method for creating a SOI CMOS type device compatible with bulk CMOS.
A related object of the present invention is to provide method for creating a SOI CMOS device compatible with bulk CMOS using a bulk CMOS physical layout data base.
Still another object of the present invention is to provide an SOI CMOS device fabricated in accordance with the foregoing objects.
SUMMARY OF THE INVENTION
According to the invention there is provided a method for creating a SOI CMOS type device compatible with bulk CMOS, which device is created using a bulk CMOS physical layout data base. The method comprises using the P-well and N-well masks used in fabrication of the bulk CMOS devices. The N-well and P-well regions are fabricated by implanting the appropriate dopants above and below the buried oxide layer to create the basic SOI CMOS structure. Particular modifications to the basic SOI CMOS structure include providing a mask for establishing ohmic contact with the wells below the buried oxide layer. This can be accomplished by the use of a separate mask which is generated from the existing bulk CMOS mask database. The mask is generated by doing the following logical AND and OR functions on the existing CMOS layers:
a) SOURCE/DRAIN [AND] P
+
[AND] P-WELL [AND] 1st CONTACT
b) SOURCE/DRAIN [AND] N
+
[AND] N-WELL [AND] 1st CONTACT
c) a) [OR] b)
Other features of the invention are disclosed or apparent in the section entitled “BEST MODE OF CARRYING OUT THE INVENTION.”
REFERENCES:
patent: 5359219 (1994-10-01), Hwang
patent: 5463238 (1995-10-01), Takahashi et al.
patent: 5641980 (1997-06-01), Yamaguchi et al.
patent: 0694977A3 (1996-01-01), None
Yoshino, A. et al: “High-speed Performance of 0.35 &mgr;m CMOS Gates Fabricated on Low-Dose SIMOC Substrates With/Without an N-Well Underneath the Buried Oxide Layer” IEEE Electron Device Letters, vol. 17, No. 3, Mar. 1, 1966 pp. 106-108.
Chen, W. et al: “Suppression of the SOI Floating-body Effects by Linked-body Device Structure” IEEE 1996 Symposium on VLSI Technology Digest of Technical Papers, 1996; pp. 92 and 93.
Advanced Micro Devices , Inc.
LaRiviere Grubman & Payne, LLP
Tran Minh Loan
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