Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-07-02
2001-08-28
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S240000, C438S253000, C438S692000
Reexamination Certificate
active
06281092
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to integrated circuits and in particular to the manufacture of a capacitor within an integrated circuit substrate. Still more particularly, the present invention relates to a method for manufacturing a metal-to-metal capacitor utilizing only a single masking step.
2. Description of the Related Art
The fabrication of an integrated circuit within a semiconductor substrate typically requires a number of processing steps, including one or more masking steps to define features of integrated circuit components. A masking step entails a number of subsidiary steps, the first of which is coating the surface of the integrated circuit with photoresist. A photolithographic mask is then precisely aligned with the semiconductor substrate and irradiated with ultraviolet light to remove portions of the photoresist and thereby define the location of a component feature. The defined location of the component feature is then selectively processed by removing material (e.g., with an etchant) or adding material (e.g., by deposition or implantation). The masking step then concludes with the removal of the photoresist.
Conventionally, the fabrication of a metal-to-metal capacitor within an analog integrated circuit has required at least two masking steps, a first masking step that defines the location of the lower plate of the capacitor and a second masking step that selectively etches the deposited capacitor dielectric. The present invention recognizes that such masking steps are some of the most expensive steps in the fabrication process, particularly considering the cost of creating the photolithographic mask and the processing time required to perform subsidiary steps like aligning the mask and exposing the photoresist. Consequently, the present invention provides an improved method of fabricating an integrated circuit capacitor that requires only a single masking step.
SUMMARY OF THE INVENTION
In accordance with the present invention, a capacitor is fabricated on a semiconductor substrate by first forming a first capacitor electrode on the semiconductor substrate and forming a planar insulating layer over the first capacitor electrode. A photoresist layer is then formed over the planar insulating layer and patterned in an only masking step to form an opening over the first capacitor electrode. Through the opening, the planar insulating layer is etched, and a capacitor dielectric layer is thereafter formed. A second capacitor electrode is then formed over the capacitor dielectric layer in alignment with the first capacitor electrode. The structure is planarized to expose the planar insulating layer. In a preferred embodiment, a trench in the second capacitor electrode is protected during planarization by a spin-on photoresist that is stripped following planarization.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Jr. Carl Whitehead
LSI Logic Corporation
Thomas Toniae M.
LandOfFree
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