CAS latency control circuit

Details CAS latency control circuit CAS latency control circuit

1999-11-09

2001-03-20

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000, C365S191000, C365S233100, C365S023000, C365S189050

Reexamination Certificate

active

06205062

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more particularly to a Column Address Strobe (CAS) latency control circuit for a memory device.
2. Background of the Related Art
In general, Dynamic Random Access Memories (DRAMs) are composed of capacitors and transistors, and are widely used as highly integrated semiconductor memories. However, because the operation of a DRAM is controlled by delaying command signals (RASB and CASB, etc.) and data therein is read in response to a Y-address signal, the DRAM has the disadvantage that data read time is long and slow. Consequently, Synchronous DRAMs (SDRAMs), have recently been developed with increased read and write speeds.
A related art CAS latency control circuit for a SDRAM will be described with reference to the attached drawings. Referring to
FIG. 1
, a related art SDRAM includes four banks BANK
0
, BANK
1
, BANK
2
, and BANK
3
, each having n main amplification units MA
0
i-MA
0
j, MA
1
i-MA
1
j, MA
2
i-MA
2
j, and MA
3
i-MA
3
j, which are secondary amplifier circuits. Each bank is further coupled to a n-bit data bus, and each of the main amplification units MA
0
i-MA
0
j, MA
1
i-MA
1
j, MA
2
i-MA
2
j, and MA
3
i-MA
3
j in each of the banks share data bus DATAi-DATAj of the same number in common. The SDRAM further includes n CAS latency control circuits CLCCi-CLCCj which are matched one to one to the data buses, such that the (i)th CAS latency control circuits share the (i)th data bus.
Chip pads in a chip are also arranged at particular locations which correspond to locations of input/output pins which are fixed in a general standard SDRAM. In
FIG. 1
, clock pads for clock inputs are arranged at a central portion of the chip, and DQ blocks DQi-DQj, which include data output buffers and pads, are positioned in a spread formation at the right side of the chip near BANK
2
and BANK
3
. They are sequenced in the order corresponding to locations of data pins. Therefore, since each of the n DQ blocks DQi-DQj includes a data buffer and an input/output pad, the DQ blocks DQi-DQj are positioned at particular locations, and the n CAS latency control circuits CLCCi-CLCCj are positioned at locations adjacent to the DQ blocks. Further, there is a one to one correspondence between the CAS latency control circuits and the DQ blocks, so that outputs of the CAS latency control circuits CLCCi-CLCCj are connected to respective DQ blocks DQi-DQj. Additionally, the positioning of the CAS latency control circuits and their respective DQ blocks is such that the distance between them is kept relatively small.
A QCLK buffer is positioned at a location adjacent to the clock pad for providing a clock signal to the CAS latency control circuits CLCCi-CLCCj, and clock signal QCLK connection lines are connected to respective CAS latency control circuits CLCCi-CLCCj.
Referring to
FIG. 2
, the related art CAS latency control circuit for a SDRAM is provided with three latches
2
,
3
, and
4
, and a controlling circuit unit
1
for controlling the three latches
2
,
3
, and
4
. Thus, controlling circuit unit
1
receives a clock signal QCLK for forwarding data, and provides control signals con
1
, con
2
, and con
3
for controlling respective latches
2
,
3
, and
4
.
First latch
2
either forwards or latches input data depending on the control signal con
3
from the controlling circuit
1
. Second latch
3
either forwards or latches the data from the first latch
2
according to the control signal con
2
from the controlling circuit unit
1
. Third latch
4
either forwards the data from the second latch
3
to an output buffer or latches the data from the second latch
3
according to the control signal con
1
from the controlling circuit unit
1
.
Referring to
FIG. 3
, each of the latches
2
,
3
, and
4
is provided with a first inverter
6
which inverts a control signal con
3
, con
2
, con
1
from the controlling circuit unit
1
. A first control inverter
5
passes data D when the control signal con
1
, con
2
, or con
3
is “low” in response to the control signal con
3
, con
2
, or con
1
and the signal from the first inverter
6
. This is in the open condition of the latch- A second inverter
8
inverts a signal from the first control inverter
5
, and a second control inverter
7
latches a data signal from the second inverter
8
when the control signal con
1
, con
2
, or con
3
is “high” in response to the control signal con
3
, con
2
, or con
1
and the signal from the first inverter
6
.
Referring to
FIG. 4
, the control inverter
5
or
7
in each of the latches is provided with first and second PMOS transistors
9
and
10
, and first and second NMOS transistors
11
and
12
between a constant supply voltage terminal and a ground voltage terminal. The second PMOS transistor
10
and the first NMOS transistor
11
receive a data signal D
in
at gates thereof, and the first PMOS
9
receives the control signal con
3
, con
2
, or con
1
from the controlling circuit unit
1
or a signal from the first inverter
6
at a gate thereof. The second NMOS transistor
12
receives the control signal con
3
, con
2
, or con
1
from the controlling circuit unit
1
or a signal from the first inverter
6
at a gate thereof, and an output terminal
13
is provided at a node of the second PMOS transistor
10
and the first NMOS transistor
11
.
FIG. 5
illustrates a first timing diagram of the related art CAS latency control circuit operation,
FIG. 6
illustrates a second timing diagram of the related art CAS latency control circuit operation,
FIG. 7
illustrates a third timing diagram of the related art CAS latency control circuit operation, and
FIG. 8
illustrates a fourth timing diagram of the related art CAS latency control circuit operation.
Referring to
FIG. 5
, the controlling circuit unit
1
provides control signals con
1
, con
2
, and con
3
all at “low” at a first rising edge of a clock signal QCLK, so that all the latches
2
,
3
, and
4
do not latch data, but instead directly bypass the data. Therefore, the output data Dout is provided at a second rising edge of the clock signal QCLK.
Referring to
FIG. 6
, the controlling circuit unit
1
provides a control signal con
1
to be applied to the third latch
4
at “high” and control signals con
2
and con
3
to be applied to the first and second latches
2
and
3
respectively at “low” at a first rising edge of a clock signal QCLK, so that the first and second latches do not latch the data. Instead, the data is passed directly to the third latch, which receives the data. Next, the controlling circuit unit
1
controls the control signal con
1
to transition from “high” to “low” at a second rising edge of the clock signal, so that the data passes through the third latch
4
and proceeds toward the data output buffer. The controlling circuit unit
1
then transitions the control signal con
1
from “low” to “high” again before a third rising edge of the clock signal, so that the data is latched at the third latch.
Referring to
FIG. 7
, the controlling circuit unit
1
holds the control signal con
3
low and control signals con
1
and con
2
high in synchronization with the clock signal QCLK. It then transitions the control signal con
1
from high to low after a second rising edge of the clock signal QCLK, and after a prescribed time period, from low to high again. The controlling circuit unit
1
causes the control signal con
2
to transition from high to low when the control signal con
1
transitions from low to high, and then from low to high at a third rising edge of the clock signal. Accordingly, the control signals con
1
and con
2
repeat the aforementioned process in a fourth rising edge of the clock signal. As the control signal is held low, the data passes through the first latch
2
to the second latch
3
, and passes through the second latch
3
to the third latch
4
when the control signal con
2
transitions to low.
In this instance, as the control signal con
2
transitions to high again, the second latch
3
l

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