Digital delay locked loop for adaptive de-skew clock generation

Details Digital delay locked loop for adaptive de-skew clock generation Digital delay locked loop for adaptive de-skew clock generation

1999-12-30

2001-08-14

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S158000, C713S401000, C710S061000

Reexamination Certificate

active

06275555

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to delay locked loop based circuits for adaptive clock generation.
BACKGROUND
As the level of integration in semiconductor integrated circuits (ICs) increases, signal delays due to parasitic resistance-capacitance loading become larger. This is especially true of high fan-out global signal lines such as synchronous clocks. Clock signals in modern programmable logic devices may drive several thousand registers. This is a considerable load to the clock driver. Clock tree structures can be implemented on chip to minimize clock skew among registers. However, the base trunk clock driver must be capable of driving this clock tree structure and, as a result, a buffer delay of several nanoseconds is typically incurred.
Circuits using phase locked loop (PLL) are widely used in data communications. An example of such a circuit may be a de-skew clock generation circuit. A typical PLL consists of three on-chip functions and a loop filter. A phase detector measures the phase and frequency difference between an external reference signal and an internal timing signal. Based on the sign and magnitude of the difference, the phase detector drives a charge pump that raises or lowers the voltage level of the loop filter. The loop filter provides a stable voltage input to a voltage controlled oscillator (VCO). The VCO develops a timing signal that is fed back to the phase detector for comparison with the incoming reference signal. When the reference signal and the VCO timing signal are identical the PLL is “locked” onto the reference signal.
A PLL based circuit may be generally sufficient where power dissipation is not an issue even though communication speeds are high. In certain circuits, communication speeds may range from Megahertz (MHz) to Gigahertz (GHz). In general, however, circuits operating at high speeds are sensitive to power dissipation that results in overheating of the circuits. In circuits where power conservation is an issue, power dissipation is also problematic. As well, problems exist with implementing a PLL in a typical integrated circuit since the PLL uses analog devices such as a phase frequency detector (PFD), charge pump and low pass filter. These problems include, among others, poor stability and performance in a noisy environment.
SUMMARY
In accordance with an embodiment of the invention, there is disclosed an apparatus including a phase detector to detect a phase difference between an output clock signal and a local reference clock signal comprising a first sampling circuit and a second sampling circuit to cross-sample the output clock signal and the local reference clock signal respectively and a comparator circuit coupled to the two sampling circuits that detects the phase difference. A digitally controlled delay line is coupled to the output clock signal to adaptively adjust a delay to compensate for the phase difference.


REFERENCES:
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5619148 (1997-04-01), Guo

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