Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-18
2001-04-03
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S301000, C257S906000, C257S907000, C257S908000
Reexamination Certificate
active
06211544
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor layouts and more particularly, to a layout for reducing interaction between storage nodes and transistors in semiconductor memory cells.
2. Description of the Related Art
Semiconductor memories such as dynamic random access memories (DRAM) typically include memory cells with storage nodes. Generally these storage nodes are formed within deep trenches etched into substrates of the semiconductor memory chip. The storage nodes are accessed using an access transistor which allows charge to be stored in the storage node or retrieves charge from the storage depending on whether the desired action is a read or write function.
In buried strap type trench capacitors, dopant outdiffusion close to a wordline can cause problems such as short channel effects in the access transistor channel.
Referring to
FIG. 1
, a layout is shown for conventional deep trench capacitors. Deep trench capacitors
10
are disposed under passing wordlines
12
. Access transistors
14
are electrically coupled to storage nodes
16
of trench capacitors
10
through diffusion regions
18
which may be either a source or a drain of access transistors
14
. Diffusion regions
20
are also included which are electrically connected to contacts
22
. Contacts
22
connect to bitline (not shown) to read and write to storage nodes
16
through access transistors
14
. Access transistors
14
are activated by wordlines
12
. When voltage is applied to wordlines
12
a channel below wordline
12
conducts allowing current to flow between diffusion regions
18
and
20
and into or out of storage node
16
.
Wordlines
12
are preferably spaced across the smallest possible distance d to conserve layout area. The smallest possible distance is typically a minimum feature size F which is achievable by the technology.
Referring now to
FIG. 2
a cross-sectional view of the layout of
FIG. 1
is shown. Elements of
FIG. 2
are labeled as described in FIG.
1
. Storage nodes
16
are isolated from a doped well
24
by a dielectric collar
26
. Shallow trench isolation
28
is provided over storage nodes
16
to electrically isolate the passing wordlines
12
formed above storage nodes
16
. Diffusion regions
18
of access transistors
14
are connected to storage node
16
by a node diffusion region
30
to a buried strap
32
. Node diffusion
30
and buried strap
32
are typically connected by outdiffusing dopants which mix to create a conductive region (node region
30
) therebetween.
In a conventional layout, the distance between wordlines
12
and buried strap
32
is usually 1F. But, if the overlay tolerance is considered, the dopant outdiffusion from buried strap
32
can potentially outdiffuse far enough to interact with a channel
34
below a gate
36
(wordline
12
) causing short channel effects in access transistor
14
. In typical layouts, an overlay tolerance is F/2, i.e., a worst case distance is F/2. A length of channel
34
is a function of diffusion regions
18
and
20
and buried strap
32
outdiffusion. Also, it is a function of the overlay tolerance between wordlines
12
and deep trenches
10
. If the dopant outdiffusion length form buried strap
32
is larger than F/2, the length of channel
34
becomes less than 1F. However, outdiffusion form buried strap
32
must generally be far enough (about F/2) to form a connection between diffusion region
18
and buried strap
32
.
As shown in phantom lines in
FIG. 2
, a worst case of misalignment between trench
10
′ and wordline
12
is shown. Further outdiffusion from buried strap
32
′ is such that channel length of channel
34
is reduced thereby causing short channel effects in access transistor
14
.
Therefore, a need exists for a layout for semiconductor memories which reduces interaction between a buried strap and an access transistor channel.
SUMMARY OF THE INVENTION
A memory cell, in accordance with the invention, includes a trench formed in a substrate, and an active area formed in the substrate below a gate and extending to the trench. The active area includes diffusion regions for forming a transistor for accessing a storage node in the trench, the transistor being activated by the gate. The gate defines a first axis wherein a portion of the active area extends transversely therefrom, the portion of the active area extending to the trench. The trench has a side closest to the portion of the active area, the side of the trench being angularly disposed relative to the gate such that a distance between the gate and the side of the trench is greater than a minimum feature size.
A memory chip layout, in accordance with the invention, includes trenches formed in a substrate, and active areas formed in the substrate. The active areas include diffusion regions for forming transistors for accessing storage nodes in the trenches. A plurality of wordlines is disposed substantially parallel to each other, the wordlines having a width and being spaced apart by a substantially same distance. The transistors each include a gate formed by the wordlines, the wordlines defining a first axis wherein a first portion of each active area extends transversely from below the wordline to a trench disposed below an adjacent wordline. The trenches have a side closest to the first portions of the active areas, the side closest of the trench being angularly disposed relative to the wordlines such that a distance between a wordline and a side closest to the first portion of a trench, disposed below an adjacent wordline, is greater than the substantially same distance between the wordlines.
Another memory chip layout includes trenches, and active areas formed in a substrate, the active areas including diffusion regions for forming transistors for accessing storage nodes in the trenches. A plurality of wordlines are disposed substantially parallel to each other, the wordlines having a width and being spaced apart by a substantially same distance. The transistors each include a gate formed by the wordlines, the wordlines defining a first axis wherein a first portion of each active area extends transversely from below the wordline to a trench disposed below an adjacent wordline. The trenches have a side closest to the first portions of the active areas, the side closest to the first portions being angularly disposed relative to the wordlines such that a distance between the wordline and the side closest to the first portions, disposed below an adjacent wordline, is greater than the substantially same distance between the wordlines. The active areas define a second axis which forms an angle with the wordlines and extends below two adjacent wordlines to connect to trenches at ends of the active areas. The trenches disposed below the two adjacent wordlines have at least on side aligned in a substantially parallel orientation relative to the second axis.
In alternate embodiments, the active areas may form an angle with the first axis such that a channel length of a channel of the access transistor disposed below the gate is greater than a width of the gate or wordlines. The trenches may have a shape including one of a rectangle, a trapezoid, a parallelogram and/or a bent rectangle. The portion (or first portion) of the active area may include a bend to further extend the distance between the gate and the side of the trench. The gate and/or the wordlines may include a width of greater than the minimum feature size to provide a longer channel length. The gate may include the width of greater than the minimum feature size only over the channels of the access transistors. The gate includes a width of the minimum feature size. The trenches below adjacent wordlines may be at least a minimum feature size apart. Pairs of wordlines adjacent on each side of the two wordlines may have active areas forming an angle opposite the rotation of the angles formed by active areas on the two wordlines, the trenches below the adjacent pairs having at least one side substantially parallel to the active areas of the adjacen
Kunkel Gerhard
Park Young-Jin
Radens Carl J.
Braden Stanton C.
Infineon Technologies North America Corp.
Nguyen Cuong Q
Thomas Tom
LandOfFree
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