Storage cell arrangement in which vertical MOS transistors...

Details Storage cell arrangement in which vertical MOS transistors... Storage cell arrangement in which vertical MOS transistors...

1998-11-02

2001-07-24

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S391000

Reexamination Certificate

active

06265748

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, generally, to a memory cell arrangement wherein the associated memory cells each include an MOS transistor which is vertical with respect to a main area of a substrate and, more particularly, to a memory cell arrangement wherein individual memory cells each include an MOS transistor vertically positioned with respect to a substrate and which possesses at least three threshold voltage values depending on the information stored therein.
2. Description of the Prior Art
In order to store large volumes of data, for example for DP (data processing) applications or for the digital storage of music or images, use is typically made of memory systems which have mechanically movable parts such as, for example, hard disk memories, floppy disks or compact discs. The moved parts are subject to mechanical wear. Furthermore, they require a comparatively large volume and permit only slow data access. Moreover, since they are sensitive to vibrations and position and have a comparatively high power consumption for their operation, these memory systems can be used in mobile systems only to a limited extent.
In order to store relatively small volumes of data, semiconductor-based read-only memories are known. These are often in the form of a planar integrated silicon circuit in which MOS transistors are used as memory cells. The transistors are selected via the gate electrode which is connected to the word line. The input of the MOS transistor is connected to a reference line and the output is connected to a bit line. During the read operation, it is assessed whether or not a current is flowing through the transistor. The logic values zero and one are assigned correspondingly. The storage of zero and one is effected in technical terms in that no MOS transistor is produced, or no conductive connection to the bit line is formed, in memory cells in which the logic value assigned to the state “no current flow through the transistor” is stored. As an alternative, MOS transistors which have different threshold voltages due to different dopant concentrations in the channel region can be formed for the two logic values.
These semiconductor-based memories permit random access to the stored information. The electrical power required to read the information is distinctly less than in the case of the abovementioned memory systems having mechanically movable parts. Since no movable parts are required, mechanical wear and sensitivity to vibrations are no longer a problem. Semiconductor-based memories can be used for mobile systems as well.
The silicon memories described generally have a planar structure. A minimum area requirement thus becomes necessary for each memory cell. Such requirement is 4 F
2
in the most favorable case, wherein F being the smallest structure size that can be produced with the respective technology.
A read-only memory cell arrangement whose memory cells include MOS transistors is disclosed in German Patent document DE 42 14 923 A1. These MOS transistors are arranged along trenches in such a way that a source region adjoins the bottom of the trench, a drain region adjoins the surface of the substrate and a channel region adjoins the side and bottom of the trench both vertically with respect to the surface of the substrate and parallel to the surface of the substrate. The surface of the channel region is provided with a gate dielectric. The gate electrode is designed as a side covering (spacer). The logic values zero and one are differentiated by different threshold voltages which are effected by channel implantation. During the channel implantation, the implanting ions impinge on the surface of the respective trench at an angle such that implantation is deliberately effected only along one side due to shading effects of the opposite side. In this memory cell arrangement, the word lines run as spacers along the sides of the trenches.
Japanese Patent document JP-A 4-226071 discloses a further memory cell arrangement which include vertical MOS transistors arranged on the sides of trenches as memory cells. In this case, diffusion regions, which in each case form the source/drain regions of the vertical MOS transistors, run on the bottom of trenches and between adjacent trenches. The word lines, which include the gate electrodes of the vertical MOS transistors, run perpendicularly to the trenches. The threshold voltage of the vertical MOS transistors is set by means of angled implantation.
U.S. Pat. No. 4,663,644 discloses a memory cell arrangement whose memory cells include vertical MOS transistors. These vertical NOS transistors are each arranged on the sides of trenches. The word lines, which each include the gate electrodes of the vertical MOS transistors, are arranged in the trenches. Two word lines are arranged in each trench. The bit lines are formed as conductor tracks on the surface of the substrate. The contact between the bit lines and the respective source/drain regions which adjoin the surface of the substrate is formed via a contact hole. The source/drain regions which adjoin the bottom of the trenches are formed as a continuous doped layer and are put at the reference potential. In this memory cell arrangement, the information is stored in the form of threshold voltages, having different levels, of the MOS transistors. The different threshold voltages are obtained by different dopant concentrations in the channel region of the MOS transistors. In order to form an increased dopant concentration in the channel region, a doped layer is deposited and is structured in such a way that sides in which increased dopant concentrations are to be formed remain covered by the structured dopant layer. The channel regions having an increased dopant concentration are formed by outdiffusion of the structured dopant layer.
In order to increase the effective storage density, it has furthermore been proposed (see, for example, the publication by Yasushi Kubota, Shinji Toyoyama, Yoji Kanic, Shuhei Tsuchimoto “Proposal of New Multiple-Valued Mask-ROM Design” IEICE Trans. Electron Vol. E77, p. 601, April 1994), to program a semiconductor memory arrangement having planar MOS transistors in the sense of multi-value logic. This procedure is also referred to as multi-level programming. In this case, the MOS transistors are produced in such a way that they have four different threshold voltage values depending on the stored information. Each of the threshold voltage values is then assigned two logic values, that is to say “0” and “0”, “0” and “1”, “1” and “0” or “1” and “1”. In this way, the effective storage density risen by a factor of two since two logic values are stored in each memory cell without the area of the memory cell changing as a result. The different threshold voltage values are obtained by different channel dopings. Masked implantation is carried out for each threshold voltage value. Four additional masks are therefore necessary for multi-level programming.
SUMMARY OF THE INVENTION
The present invention is thereof directed to specifying a semiconductor-based memory cell arrangement in which an increased storage density in achieved and which can be produced with both few production steps and a high yield. Furthermore, it is intended to specify a method for the production of such a memory cell arrangement.
In the memory cell arrangement according to the present invention, memory calls which each comprise an MOS transistor which is vertical with respect to the main area are provided in a substrate. A substrate made of monocrystalline silicon or the silicon layer of an SOI substrate is preferably used as the substrate. The vertical MOS transistors each have one of at least three threshold voltage values depending on the stored information. The memory cell arrangement is programmed in the sense of multi-value logic.
One of the different threshold voltage values is obtained by virtue of the fact that the corresponding MOS transistors have a gate dielectric having a thickness differing from the other MOS transist

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