Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-11-30
2001-04-03
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S202000
Reexamination Certificate
active
06212614
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory management system and more particularly to memory management system which can be used with a software emulator which meets MIL-STD-1750A with respect to paging and protection attributes, such as block protection and access lock and key functions.
2. Description of the Prior Art
It is known that microprocessors are configured with different instruction set architectures (ISA). The ISA determines the instruction set for a particular microprocessor. Application programs are executed by the microprocessors normally written in relatively high level language, which is compiled into machine instructions compatible with the instruction set for the specific microprocessor. Microprocessors are increasingly being designed to execute instructions faster and faster. As such, systems incorporating such microprocessors are often upgraded to increase the speed of the system. Unfortunately, depending on the particular upgrade, often times the instruction set of the upgrade microprocessor is incompatible with the instruction set of the microprocessor to be replaced (“legacy microprocessor”). As such, in such applications, the existing application programs often need to be rewritten in new and modem computer languages with modem compilers. Unfortunately, such an undertaking can be quite cumbersome and expensive.
Due to the age and obsolescence of many existing avionic onboard computers, the reliability of such computers is rapidly declining while maintenance is becoming more difficult and costly to achieve. As such, it is sometimes required to replace outdated “legacy” microprocessors with newer technology “native” microprocessors. To work around instructions set incompatibilities, emulation systems (emulators) have been developed. Emulators are known which emulate the instructions set of the legacy microprocessor in order to enable the instructions of the legacy microprocessor to be “executed” by a different microprocessor. Both software and hardware based emulators are known. For example, various software emulators for the F-16 avionics integration support facility (AISF) common modular environment (COMET) are described in document no. F-16AISF-COMET-100 (EMULATORS-SWD-A, dated May 21, 1996). Hardware based emulators for military standard MIL-STD-1750A, are discussed in the document entitled Line Replaceable Unit Emulator Hardware Product Fabrication Specification, document no. SFF20702 dated Apr. 16, 1996.
Unfortunately, known software emulators have been known to be relatively inefficient. In particular, in such known software emulators, legacy instructions are fetched or the upgrade microprocessor which uses a look up table to interpret the legacy instruction. Since each legacy instruction must be interpreted, computer systems which incorporate cache memory are known to suffer from relatively high probability of cache misses which decreases the overall throughput of the system.
Another problem with such software emulators is the need to comply with MIL-STD-1750A with respect to memory management. As used herein MIL-STD-1750A refers to “Military Standard Sixteen Bit Computer Instruction Set Architecture”, dated Jul. 2, 1980, hereby incorporated by reference. MIL-STD-1750A sets forth a virtual paging and protection scheme that maps sixteen (16) 64K word logical operand spaces and sixteen (16) 64K word logical instruction spaces into 1 M word of physical memory. Each 64K word logical space is controlled by sixteen (16) logical page registers which control the logical to physical mapping as well as the protection attributes, such as execute protect and write protect, as well as an access lock and key functions. Block protection is specified for physical memory in blocks of 1K word size. Block protection over-rides page register protection. In other words, if the block is write protected, it is write protected regardless of the write protection setting in the page registers.
To accurately model the protection attributes in a software emulator, each operand access and each instruction access require software to look up the current settings for the page register and determine the protection. If the attribute enables access, then the access is performed, otherwise a fault is generated. Such protection attributes are known to seriously degrade the performance of such software emulators. Thus, there is a need to efficiently implement paging and block protect, and lock and key functions which meet MIL-STD-1750A for a software emulator.
SUMMARY OF THE INVENTION
Briefly the present invention relates to a system and method for implementing the paging and protection attributes, such as block protection and access lock and key functions promulgated in MIL-STD-1750A. The present invention takes advantage of the PowerPC microprocessor architecture to implement the paging and protection attributes required by MIL-STD-1750A in hardware. Since the paging and the protection attributes are implemented in hardware, the system performance is greatly improved.
REFERENCES:
patent: 4276594 (1981-06-01), Morley
patent: 4760525 (1988-07-01), Webb
patent: 5079737 (1992-01-01), Hackbarth
patent: 5548746 (1996-08-01), Carpenter
patent: 5822749 (1998-10-01), Agarwal
patent: 5956752 (1999-09-01), Mathews
Cannon William J.
Hoerig Timothy R.
Coleman Eric
TRW Inc.
Yatsko Michael S.
LandOfFree
Legacy MIL-STD-1750A software emulator address translation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Legacy MIL-STD-1750A software emulator address translation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Legacy MIL-STD-1750A software emulator address translation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2504636