Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
1998-12-31
2001-08-14
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S503000, C710S022000
Reexamination Certificate
active
06275242
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of direct memory access transfers in a computer system. More particularly, this invention pertains to the field of terminating direct memory transfers between system memory and a video device.
BACKGROUND OF THE INVENTION
Video devices such as Digital Versatile Disc (DVD) decoders are now being regularly included in computer systems. Such decoders receive an encoded input and produce a decoded and displayable output. In a typical computer system, a stream of encoded information is moved from a storage device such as a DVD drive to system memory. From system memory, the encoded information is moved through a graphics controller and to a decoding device. The movement of encoded information from system memory to the decoding device typically occurs via direct memory access (DMA) under control of the graphics controller. The graphics controller also allows read and write cycles to the decoding device for configuration or status checking purposes. The graphics controller typically allows the DMA transfers and the read and write cycles to be interwoven, with the read and write cycles having precedence over the DMA transfers. For computer systems with an Accelerated Graphics Port (AGP) architecture, the size of the DMA transfers from system memory to the decoding device may be as large as 2 Mbytes. The transfer is performed as a series of 32 byte cycles on the AGP.
An undesirable situation occurs when a configuration cycle needs to be performed and the graphics controller is in the process of streaming a large amount of encoded information to the decoding device. 2 Mbytes of encoded video information may represent 1-2 seconds of real time video. The configuration cycle may be a result of an computer user requesting that the video pause, rewind, fast forward, stop, etc. Unless there is a way to abort the current DMA transfer, the user will experience a 1-2 second delay in response time. Further, the DMA transfer must be terminated properly so as to not violate the various bus protocols. For example, on AGP, once a read cycle has been initiated by an AGP agent, the agent must be able to receive the returned information when it is delivered. There is no mechanism on AGP to abort a read cycle once the read request has been issued.
The above mentioned issue could be solved by limiting the size of DMA transfers. However, this increases the amount of system overhead required to move the encoded information from system memory to the decoding device, which may result is visual quality degradation due to possible skipped frames.
SUMMARY OF THE INVENTION
A method and apparatus for terminating direct memory access transfers from system memory to a video device is disclosed. The method includes halting at least one pending direct memory access write cycle to the video device as well as allowing an uninterrupted read and write access to the video device. The method also includes completing a current direct memory access read cycle from a memory device and resetting a direct memory access register and a temporary storage location.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
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Hall Cliff D.
Roedel Andrew E.
Shah Nilesh V.
Chauhan Ulka J.
Intel Corporation
Wells Calvin E.
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