Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-03-09
2001-08-28
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C430S005000
Reexamination Certificate
active
06282696
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to photolithography techniques. More particularly, the invention relates to improved methods and apparatuses for performing optical proximity correction techniques in a computationally efficient manner and with particular regard to mitigating optical distortions caused by topographically varying wafer surfaces.
The minimum feature sizes of integrated circuits (ICs) have been shrinking for years. Commensurate with this size reduction, various process limitations have made IC fabrication more difficult. One area of fabrication technology in which such limitations have appeared is photolithography.
Photolithography involves selectively exposing regions of a resist coated silicon wafer to a radiation pattern, and then developing the exposed resist in order to selectively protect regions of wafer layers (e.g., regions of substrate, polysilicon, or dielectric).
An integral component of photolithographic apparatus is a “reticle” which includes a pattern corresponding to features at a layer in an IC design. Such reticle typically includes a transparent glass plate covered with a patterned light blocking material such as chromium. The reticle is placed between a radiation source producing radiation of a pre-selected wavelength and a focusing lens which may form part of a “stepper” apparatus. Placed beneath the stepper is a resist covered silicon wafer. When the radiation from the radiation source is directed onto the reticle, light passes through the glass (regions not having chromium patterns) and projects onto the resist covered silicon wafer. In this manner, an image of the reticle is transferred to the resist.
The resist (sometimes referred to as a “photoresist”) is provided as a thin layer of radiation-sensitive material that is spin-coated over the entire silicon wafer surface. The resist material is classified as either positive or negative depending on how it responds to light radiation. Positive resist, when exposed to radiation becomes more soluble and is thus more easily removed in a development process. As a result, a developed positive resist contains a resist pattern corresponding to the dark regions on the reticle. Negative resist, in contrast, becomes less soluble when exposed to radiation. Consequently, a developed negative resist contains a pattern corresponding to the transparent regions of the reticle. For simplicity, the following discussion will describe only positive resists, but it should be understood that negative resists may be substituted therefor. For further information on IC fabrication and resist development methods, reference may be made to a book entitled
Integrated Circuit Fabrication Technology
by David J. Elliott, McGraw Hill, 1989.
One problem associated with photolithography is that light passing through a reticle is refracted and scattered by the chromium edges. This causes the projected image to exhibit some rounding and other optical distortion. The problems become especially pronounced in IC designs having feature sizes near the wavelength of light used in the photolithographic process.
To remedy this problem, a reticle correction technique known as optical proximity correction (“OPC”) has been developed. Optical proximity correction involves adding dark regions to and/or subtracting dark regions from a reticle design at locations chosen to overcome the distorting effects of diffraction and scattering. Typically, OPC is performed on a digital representation of a desired IC pattern. First, the digital pattern is evaluated with software to identify regions where optical distortion likely will result. Then the optical proximity correction is applied to compensate for the distortion. The resulting pattern is ultimately transferred to the reticle glass.
FIGS. 1A through 1D
will now be described to illustrate the OPC process.
FIG. 1A
shows a hypothetical reticle
100
corresponding to an IC layout pattern. For simplicity, the IC pattern consists of three rectangular design features. A clear reticle glass
110
allows radiation to project onto a resist covered silicon wafer. Three rectangular chromium regions
102
,
104
and
106
on reticle glass
110
block radiation to generate an image corresponding to intended IC design features.
As light passes through the reticle, it is refracted and scattered by the chromium edges. This causes the projected image to exhibit some rounding and other optical distortion. While such effects pose relatively little difficulty in layouts with large feature sizes (e.g., layouts with critical dimensions above about 1 micron), they can not be ignored in layouts having features smaller than about 1 micron.
FIG. 1B
illustrates how diffraction and scattering affect an illumination pattern produced by radiation passing through reticle
100
and onto a section of silicon substrate
120
. As shown, the illumination pattern contains an illuminated region
128
and three dark regions
122
,
124
, and
126
corresponding to chromium regions
102
,
104
, and
106
on reticle
100
. The illuminated pattern exhibits considerable distortion, with dark regions
122
,
124
, and
126
having their corners rounded and their feature widths reduced. Other distortions commonly encountered in photolithography (and not illustrated here) include fusion of dense features and shifting of line segment positions. Unfortunately, any distorted illumination pattern propagates to a developed resist pattern and ultimately to IC features such as polysilicon gate regions, vias in dielectrics, etc. As a result, the IC performance is degraded or the IC becomes unusable.
FIG. 1C
illustrates how optical proximity correction may be employed to modify the reticle design shown in FIG.
1
A and thereby better provide the desired illumination pattern. As shown, a corrected reticle
140
includes three base rectangular features
142
,
144
, and
146
outlined in chromium on a glass plate
150
. Various “corrections” have been added to these base features. Some correction takes the form of “serifs”
148
a
-
148
f
and
149
a
-
149
f
. Serifs are small appendage-type addition or subtraction regions typically made at corner regions on reticle designs. In the example shown in
FIG. 1C
, the serifs are square chromium extensions protruding beyond the corners of base rectangles
142
,
144
, and
146
. These features have the intended effect of “sharpening” the corners of the illumination pattern on the wafer surface. In addition to serifs, the reticle
140
includes segments
151
a
-
151
d
to compensate for feature thinning known to result from optical distortion.
FIG. 1D
shows an illumination pattern
160
produced on a wafer surface
160
by radiation passing through the reticle
140
. As shown, the illuminated region includes a light region
168
surrounding a set of dark regions
162
,
164
and
166
which rather faithfully represent the intended pattern shown in FIG.
1
A. Note that the illumination pattern shown in
FIG. 1B
of an uncorrected reticle has been greatly improved by use of an optical proximity corrected reticle.
The OPC process is generally performed by scanning a digitized version of an IC layout design to identify feature dimensions, interfeature spacing, feature orientation, etc. The scanning process may proceed across the IC layout design in a rasterized fashion to cover the entire pattern. In some IC layout designs, it may also be necessary to conduct raster scans in the two or more directions (e.g., horizontal, vertical, and one or more diagonal directions). In some cases, the OPC computations may include generating a detailed computer model of a reticle image known as a Fast Aerial Image of Mask (FAIM). This image is then itself evaluated to determine where to make reticle corrections.
For more information on OPC scanning techniques, reference may be made to U.S. patent application Ser. No. 08/607,365 now U.S. Pat. No. 5,723,233, issued Mar. 3, 1998 entitled “Optical Proximity Correction Method And Apparatus”, and assigned to LSI Logic Corporation, the assignee of the pr
Chao Keith K.
Eib Nicholas K.
Garza Mario
Jensen John V.
Beyer Weaver & Thomas
LSI Logic Corporation
Smith Matthew
Thompson A. M.
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