Static semiconductor memory device

Details Static semiconductor memory device Static semiconductor memory device

1999-06-10

2001-01-02

Monin, Jr., Donald L. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S393000, C257S904000, C365S154000

Utility Patent

active

06169313

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static semiconductor memory device (hereinafter abbreviated as an SRAM).
2. Description of the Background Art
Recently, energy conservation and low voltage operation of the semiconductor device included in a portable apparatus have become a growing concern for extending a lasting time of a battery included in the portable apparatus. Accordingly, the demand for an SRAM capable of performing the low voltage operation with reduced amount of power consumption is increasing. An SRAM memory cell for the low voltage operation generally includes six transistors and, in most cases, what is called a full CMOS (Complementary Metal Oxide Semiconductor) memory cell is used.
FIG. 12
is an equivalent circuit diagram of the SRAM memory cell. Referring to
FIG. 12
, the equivalent circuit of the SRAM memory cell includes: access transistors
1
a
and
1
b
of n type transistors; driver transistors
2
a
and
2
b
of n type transistors; load transistors
3
a
and
3
b
of p type transistors; bit lines
4
a
and
4
b
; a word line
5
; and storage nodes
6
a
and
6
b
. Driver transistors
2
a
and
2
b
and load transistors
3
a
and
3
b
form a flip-flop circuit in the memory cell.
Next, two conventional examples will be described.
First, a layout pattern of an SRAM memory cell used in a first conventional example is shown in FIG.
13
. In
FIG. 13
, a region of one memory cell is defined by a dotted line. Formed in one memory cell region are isolation insulating films
11
a
to
11
c
, n type active regions
12
a
to
12
f
, p type active regions
12
g
to
12
j
, and polycrystalline silicon interconnections to be interconnections for gate electrodes or interconnections (hereinafter shown as polycrystalline silicon interconnections)
13
a
to
13
c
for a layered structure of polycrystalline silicon and silicide. Further, first layer metal interconnections
15
a
to
15
c
and first contacts
14
a
to
14
h
connecting the active regions and polycrystalline silicon interconnections to the first layer metal interconnections are formed. Second layer metal interconnections
17
a
to
17
d
and second contacts
16
a
to
16
d
connecting the active layers and second layer metal interconnections are also formed.
Next, each portion of the equivalent circuit of the SRAM memory cell shown in
FIG. 12
will be described with reference to FIG.
13
. It is noted that, for an access transistor, active regions connected to the bit line and driver transistor are hereinafter conveniently referred to as drain and source active regions, respectively.
Access transistor
1
a
includes drain active region
12
a
, interconnection
13
a
for a gate electrode and source active region
12
b
, whereas access transistor
1
b
includes drain active region
12
d
, interconnection
13
a
for gate electrode and source active region
12
e
. Driver transistor
2
a
includes drain active region
12
b
, interconnection
13
b
for gate electrode and source active region
12
c
, whereas driver transistor
2
b
includes drain active region
12
e
, interconnection
13
c
for gate electrode and source active region
12
f
. Load transistor
3
a
includes drain active region
12
g
, interconnection
13
b
for gate electrode and source active region
12
h
, whereas load transistor
3
b
includes drain active region
12
i
, interconnection
13
c
for gate electrode and source active region
12
j.
Further, each of bit lines
4
a
,
4
b
and word line
5
shown in
FIG. 12
correspond to interconnections
17
a
,
17
b
and
13
a
in FIG.
13
. Interconnection
15
c
in
FIG. 13
corresponds to a Vcc interconnection, and interconnections
17
c
and
17
d
correspond to GND interconnections.
Contacts
14
a
,
14
c
and
14
e
in
FIG. 13
correspond to a group of contacts of storage node
6
a
which are mutually connected at a first layer metal interconnection
15
a
, and contacts
14
b
,
14
d
and
14
f
correspond to a group of contacts of storage node
6
b
which are mutually connected at first layer metal interconnection
15
b.
FIG. 14
is a cross sectional view taken along the line I—I in FIG.
13
.
FIG. 14
mainly shows a silicon substrate
21
, a p type well
20
p
, n
−
active regions
23
a
to
23
d
, silicon oxide films
24
a
to
24
d
which are sidewall insulation layers of the transistors, and interlayer insulation films
25
a
and
25
b
. The other parts of the structure which are denoted by reference characters in
FIG. 14
correspond to those denoted by the same reference characters in FIG.
13
. Therefore, description thereof is not repeated.
A layout pattern of an SRAM memory cell used in a second conventional example is shown in FIG.
15
. The second conventional example is different from the first conventional example in that first contacts
14
i
and
14
j
generally include a structure which is called a shared contact. The shared contact connects a polycrystalline silicon interconnection, active region and first layer metal interconnection together with one contact. In other words, although n type active region
12
b
and interconnection
13
c
are connected to interconnection
15
a
through two contacts
14
a
and
14
c
in
FIG. 13
, they are connected to interconnection
15
a
through one contact
14
i
in FIG.
15
. This is the same for contact
14
j
in FIG.
15
.
If the shared contact is used, reduction in a cell size is generally achieved as the number of contacts decreases.
For the above described memory cell of the second conventional example, a highly skilled technique is required to ensure overlay accuracy for photolithography as the first metal interconnection is simultaneously connected to both of the polycrystalline silicon interconnection and active region with one contact by using the shared contact. The memory cell of the first or second conventional example is selected in accordance with equipment performance in each manufacturing factory.
The above described full CMOS type SRAM memory cell suffers from the following four problems.
The first problem is associated with the second conventional example, and is that although the shared contact allows reduction in the cell size as compared with the memory cell of the first conventional example, it makes the low voltage operation more difficult as compared with the first conventional example.
The reason which has been found for the first time will now be described.
FIG. 15
shows a relation between the memory cell pattern of the second conventional example and cell current during reading operation. The cell current flows from a bit line load to a GND through the bit line and the storage node on the Low side. When storage node
6
a
in
FIG. 14
is at the Low level, current I
1
shown in
FIG. 15
flows and, when storage node
6
b
in
FIG. 12
is at the Low level, current I
2
shown in
FIG. 15
flows. Here, only current I
1
flows through a portion defined by a relatively narrow width W
1
between polycrystalline silicon interconnection
13
c
and isolation insulation film
11
a
in a current path. Generally, however, W
1
hardly affects a current value of current I
1
, and current values I
1
and I
2
are almost equal.
On the other hand, when a mask for the polycrystalline silicon interconnection is displaced with respect to the isolation insulation film in direction toward a top portion of the sheet of the drawing, a width W
2
corresponding to the above mentioned W
1
becomes extremely narrow. Thus, for the cell current values, I
1
decreases as compared with I
2
. This may result in imbalance characteristic of the memory cell and the memory cell operation at the low level becomes worst. More specifically, shortage of current on the side of I
1
makes it difficult for storage node
6
a
to attain to the Low level.
On the other hand, for the memory cell of the first conventional example in
FIG. 13
, a maximum voltage for operation is better than that of the second conventional example as the cell current is not reduced by displacement of the mask.
The

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