Method and structure for etching a thin film perovskite layer

Details Method and structure for etching a thin film perovskite layer Method and structure for etching a thin film perovskite layer

1998-12-22

2001-01-23

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S710000, C438S712000, C438S722000

Reexamination Certificate

active

06177351

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to electronic devices, and more specifically to methods and structures for incorporating thin film perovskite layers into semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
Increasing demand for semiconductor memory and competitive pressures require higher density integrated circuit dynamic random access memories (DRAMs) based on one-transistor, one-capacitor memory cells. But scaling down capacitors with the standard silicon oxide and nitride dielectric presents problems including decreasing the quantity of charge that may be stored in a cell. Consequently, alternative dielectrics with dielectric constants greater than those of silicon oxide and nitride are being investigated. Various dielectric materials are available, such as tantalum pentoxide (dielectric constant about 25 versus silicon nitride's dielectric constant of about 7) as described in Ohji et al., “Ta
2
O
5
capacitors' dielectric material for Giga-bit DRAMs,” IEEE IEDM Tech. Dig. 5.1.1 (1995); lead zirconate titanate (PZT), which is a ferroelectric and supports nonvolatile charge storage (dielectric constant of about 1000), described in Nakamura et al., “Preparation of Pb(Zr,Ti)O
3
thin films on electrodes including IrO
2
, 65 Appl. Phys. Lett. 1522 (1994); strontium bismuth tantalate (also a ferroelectric) described in Jiang et al. “A New Electrode Technology for High-Density Nonvolatile Ferroelectric (SrBi
2
Ta
2
O
9
) Memories,” VLSI Tech. Symp. 26 (1996); and barium strontium titanate (dielectric constant about 500), described in Yamamichi et al., “An ECR MOCVD (Ba,Sr)TiO
3
based stacked capacitor technology with RuO
2
/Ru/TiN/TiSi
X
, storage nodes for Gbit-scale DRAMs,” IEEE IEDM Tech. Dig. 5.3.1 (1995), Yuuki et al., “Novel Stacked Capacitor Technology for 1 Gbit DRAMs with CVD-(Ba,Sr)TiO
3
Thin Films on a Thick Storage Node of Ru,” IEEE IEDM Tech. Dig. 5.2.1 (1995), and Park et al., “A Stack Capacitor Technology with (Ba,Sr)TiO
3
Dielectrics and Pt Electrodes for 1 Giga-Bit density DRAM, VLSI Tech. Symp. 24 (1996). Also see Dietz et al., “Electrode influence on the charge transport through SrTiO
3
thin films, 78 J. Appl. Phys. 6113 (1995), (describes electrodes of Pd, Au, and so forth on strontium titanate); U.S. Pat. No. 5,003,428 (PZT and barium titanate), U.S. Pat. No. 5,418,388 (BST, SrTiO
3
, PZT, etc.), and U.S. Pat. No. 5,566,045 (thin Pt on BST).
These alternative dielectrics are typically deposited at elevated temperatures and in an oxidizing ambient. As a result, an oxygen-stable bottom electrode material such as platinum or ruthenium oxide is used. Platinum, however, readily forms a silicide when in direct contact with silicon, and further is not a good barrier to oxygen due to fast diffusion down the platinum grain boundaries. In U.S. Pat. No. 5,504,041, Summerfelt uses a conductive nitride barrier layer beneath a platinum electrode to inhibit diffusion of oxygen to an underlayer susceptible to oxidation. Another problem with platinum electrodes is that the adhesion of platinum to silicon dioxide, silicon nitride, and other common interlayer dielectric materials is poor. Platinum structures that are patterned and etched tend to debond during subsequent processing. U.S. Pat. Nos. 5,489,548; 5,609,927; and 5,612,574 propose the use of an adhesion layer to prevent the debonding of the platinum electrode.
Some of these alternative dielectrics, such as PZT, BST, and SBT are ferroelectrics, and hence may be used as the storage element in ferroelectric non-volatile RAMs (FRAM). An FRAM cell is similar to a DRAM cell, except that the polarization of the ferroelectric material is used to indicate the data content of the cell in an FRAM, while electrical charge in the material indicates the data content of the cell in a DRAM. The charge in the DRAM dissipates, while the polarization of the material is non-volatile.
Many of these alternative dielectrics, such as PZT, BST, and SBT, are also perovskites. The etching of thin film perovskite materials with current dry processing techniques, however, can be difficult and can degrade important material properties. For example, plasma etching processes typically use one or more halogen or halogenated gases (e.g. chlorine, fluorine, CF
4
), usually at elevated temperatures (generally greater than about 400° C., and typically about 500-800° C.), to chemically etch perovskite materials. While lower temperatures can be used, the high temperature is generally conducive to removing the species due to the low vapor pressure of the metal-halogen compounds. Other dry etching processes are also used to etch perovskite materials, such as ion milling with a noble gas (e.g. argon). This type of process primarily etches by physical instead of chemical or reactive phenomenon. Purely physical ion milling can generally etch even hard to etch materials such as perovskites, but it is not selective only to the perovskite material. Some dry etch processes (e.g. reactive ion milling) may comprise elements from both chemical and physical methods of removing material.
Generally, one common problem with current dry etching process techniques for thin film perovskites is insufficient selectivity between the perovskite material and the substrate or the other materials on the substrate, such as the mask layer over the perovskite or the etch stop layer under the perovskite. Another common problem is that the etched surface of the perovskite layer (or other layers) can be damaged by the dry etch process, either through changes in point defect chemistry, or through the redeposition of etched material.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the invention, there is disclosed a method for etching a thin film perovskite layer overlying a second material without substantially etching the second material. The method comprises forming a substantially-silicon-free dielectric etchstop layer on a second dielectric layer comprising silicon, depositing the perovskite layer over the etchstop layer, forming a mask layer over the perovskite layer, patterning and removing portions of the mask layer to form a desired pattern, and etching portions of the perovskite layer not covered by the mask layer, whereby the etching stops on the etchstop layer. In further embodiments a conductive layer is formed over the perovskite layer before the mask layer is formed, and the etching removes portions of the conductive layer not covered by the hardmask.
In accordance with another preferred embodiment of the invention, there is disclosed a microelectronic structure. The structure comprises a substantially-silicon-free dielectric etchstop layer overlying a second dielectric layer comprising silicon, and a perovskite layer having a desired pattern and comprising an etched side overlying a substantially unetched portion of the etchstop layer. In further embodiments, the structure is a capacitor, and the etchstop layer comprises aluminum.
An advantage of the inventive concepts is that the etch stop layer inhibits removal of the second dielectric layer, which is typically etchable by the perovskite layer etch.


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