Peripheral structure of a chip as a semiconductor device,...

Details Peripheral structure of a chip as a semiconductor device,... Peripheral structure of a chip as a semiconductor device,...

1999-06-10

2001-04-03

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S627000, C438S643000, C438S618000

Reexamination Certificate

active

06211070

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices such as integrated circuits and manufacturing method thereof. More specifically, it relates to a peripheral structure of each chip as a semiconductor device, and improvement of the manufacturing method thereof.
2. Description of the Background Art
Recently, the degree of integration of semiconductor integrated circuits has been much improved. As the degree of integration increases, the diameter of contact holes is made smaller, and impurity regions are formed shallower. Further, as the number of interconnection layers increase and provided in the form of multiple layers, inter-insulating layers insulating the interconnection layers from each other are stacked thick one after another. Consequently, the aspect ratio (depth/diameter) of the contact hole is increased.
Conventionally, an interconnection layer of aluminum•silicon (AlSi) or the like has been deposited by sputtering. However, because of directivity of plasma, a contact hole can not be covered by a film of uniform thickness by sputtering. Especially at sidewall portions and bottom portion of the contact hole, the interconnection layer becomes thin. Therefore, if the sidewall portion of the contact hole becomes steep, the interconnection layer is disconnected at the sidewall portion and the bottom portion.
In order to avoid the above described problem, recently a tungsten (W) plug utilizing CVD (Chemical Vapor Deposition) method has been developed. Reduction of tungsten hexafluoride (WF
6
) using hydrogen (H
2
) or silane (SiH
4
) have been known as methods for forming a tungsten thin film by using the CVD method. Respective reaction formulas for reduction of WF
6
are as follows:
WF
6
(g)+3H
2
(g)→W(s)+6HF(g)
2WF
6
(g)+3SiH
4
(g)→2W(s)+3SiF
4
(g)+6H
2
(g)
where (g) and (s) denote gas phase and solid phase, respectively.
The CVD-tungsten plug forming technique includes selective tungsten formation and etchback tungsten plug formation. Selective tungsten formation refers to a technique in which tungsten is grown or applied only in the contact hole, and for this reason, it is regarded as an ideal technique of filling. However, it has not yet been practically utilized because of the following reasons.
One reason is that the growth or application of tungsten in selective tungsten formation is sensitive to the surface condition. In selective tungsten formation, since growth of tungsten is sensitive to the surface condition, the growth reaction of tungsten differs dependent on underlayers. More specifically, when contact holes are formed not only on n type and p type impurity layers but also on underlayers such as n type and p type polysilicon (poly-Si) layer, tungsten polycide (WSi
x
/poly-Si) layer and titanium silicide (TiSi
2
) layer, it is difficult to uniformly fill all these contact holes formed on different underlayers. In addition, the depth of a contact hole with the silicon substrate being the underlying layer is different from the depth of a contact hole with a polysilicon layer being the underlying layer because of the thickness of polysilicon layer stacked on the substrate, and hence it is impossible to uniformly fill these contact holes.
Secondary, growth of tungsten is also sensitive to the surface condition of the insulating film in selective tungsten formation. More specifically, if there is a little residue or damage of the preceding steps left on the insulating film, such portion becomes a nuclear formation site, on which tungsten grows and will adhere. In this manner, a phenomenon of “lost selectivity” occurs and tungsten grows and remains not only in the contact holes but also on the insulating film.
From these reasons, selective tungsten formation is not practical.
Etchback tungsten plug formation refers to a technique in which a barrier metal such as titanium nitride (TiN) or titanium tungsten (TiW) is formed as a glue layer. A tungsten film is deposited entirely over the wafer and the tungsten is etched back entirely to leave tungsten plugs in contact holes. Compared with the aforementioned selective tungsten formation, the etchback tungsten plug formation is relatively easy, and practical application is expected. A conventional semiconductor device manufactured by using the etchback tungsten plug formation and manufacturing method thereof will be described in the following.
First, the structure of the conventional semiconductor device will be described.
FIG. 29
is a plan view schematically showing a conventional wafer.
FIG. 30
is an enlarged plan view showing a portion B of FIG.
29
. Referring to these figures, a plurality of devices regions
260
are formed on the wafer
300
. Device regions
260
are manufactured through etchback tungsten plug process. Dicing line portions
250
at which device regions are not formed exist between device regions
260
. Alignment marks
220
are formed on dicing line portion
250
. Alignment mark
220
is a projecting mark. Dicing line portion
250
is the region which is cut when wafer
300
is divided into chips, and it is cut along the line j—j, for example.
FIG. 31
is a partial cross section taken along the line n—n of
FIG. 30
, and
FIG. 32
is a partial cross section taken along the line o—o of FIG.
30
.
FIG. 31
shows a cross section of a portion where the alignment mark is not formed on the dicing line. Before cutting at dicing, dicing line portion
250
exists between device forming regions
260
. As to the device forming region
260
, an oxide film
203
for isolating element is formed on the surface of a semiconductor substrate
202
. Between the oxide films
203
, an MOS transistor
230
is formed. The MOS transistor
230
includes a gate electrode
204
, a gate oxide film
205
and an impurity diffused region
206
. An insulating layer
207
is formed on the surface of semiconductor substrate
202
in the device forming region
260
. Insulating layer
207
has an opening
252
above the impurity diffused region
206
. The surface of a portion of impurity diffused region
206
is exposed through this opening
252
. A barrier metal
208
is formed thin in the periphery of the insulating layer
207
, and at the sidewall portions and the bottom portion of the openings
252
. The barrier metal
208
is formed of TiN/Ti. The opening
252
of insulating layer
207
is filled with a tungsten plug
201
b.
On the surface of insulating layer
207
and on tungsten plug
201
, a first aluminum interconnection layer
209
is formed. The first aluminum interconnection layer
209
is electrically connected to impurity diffused region
206
through tungsten plug
201
b.
An interlayer insulating film
210
is formed on the surface of insulating layer
207
on which the first aluminum interconnection layer
209
is formed. A through hole
253
is provided in interlayer insulating film
210
on the first aluminum interconnection layer
209
. A portion of the surface of the first aluminum interconnection layer
209
is exposed through this through hole
253
. On the interlayer insulating film
210
, a second aluminum interconnection layer
211
is formed. The second aluminum interconnection layer
211
is electrically connected to the first aluminum interconnection layer
209
through the through hole
253
of the interlayer insulating film
210
. A passivation film
212
is formed to cover the surface of the second aluminum interconnection layer
211
. The passivation film
212
has an opening. Through this opening, a portion of the surface of the second aluminum interconnection layer
212
is exposed, thus forming a bonding pad portion
213
.
As to the dicing line portion
250
, there is nothing formed on the surface of semiconductor substrate
202
, and the surface of semiconductor substrate
202
is made rough because of etchback carried out to form the tungsten plug
201
b.
For simplicity, part of the dicing line portion
250
is not shown in the figure.
FIG. 32
is a cross section of a portion where an alignm

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