Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-10-31
2001-09-25
Beausoleil, Robert (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S108000, C710S108000, C713S324000
Reexamination Certificate
active
06295566
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computer system having a PCI bus, and more specifically to expansion of a PCI-to-PCI bridge subsystem of a computer system.
2. Description of the Related Art
Computer systems often include a large number of peripheral devices and other components distributed on one or more buses. The Peripheral Component Interconnect (PCI) bus, a local bus standard developed by Intel Corporation and the PCI Special Interest Group, is one of the industry's most prevalent buses and a de facto standard. Because PCI allows independent bus mastering off the main processor, data rates are enormously increased over other bus standards since many processes can be off-loaded to bus masters other than the processor.
The ease of processing parallelism inherent in PCI bus systems has lead many product manufacturers to support PCI. PCI devices, fabricated on PCI expansion cards, have been manufactured independently of the processor and of the endian scheme. Many new products are fabricated on insertable cards, which a user inserts into a computer system by identifying a vacant slot in a bus, powering down the computer system inserting the card, and powering back up the computer system to allow the configuration of the new device. The PCI bus approach allows expansion of computer systems by insertion of cards or other components into slots on one of the buses. The processor local bus is typically a high-speed bus on which the CPU, main memory, and other vital components are connected. Devices on one PCI bus can communicate with devices on another PCI bus via a bridge connecting the respective buses.
PCI allows a tree-like device distribution in which one or more PCI buses are connected by PCI bridges to a processor local bus. PCI also allows straightforward operating system configuration, as each PCI bus systems configure (i.e., assign resources to) devices to allow the devices to communicate with the processor. PCI configuration is automatic upon power-up; in fact, autoconfiguration is one of the significant advantages of the PCI approach. Traditionally, however, the configuration typically occurs only at power up, to prevent the system from having to poll slots and configure devices as a background task, and from requiring a dedicated interrupt. Because resources are limited, hot or dynamic reconfiguration typically does not allow insertion of new devices of unknown type into PCI bus slots. Therefore, power must be disabled to the computer system when a PCI card is inserted, removed, or moved from one slot to another. Each PCI device, including PCI-to-PCI bridges, contains 64 double-word registers of configuration space. The first 16 doublewords are reserved for a configuration header, including a vendor identifier and device type. The remaining 48 doublewords are available for device-specific features. Upon power-up, the configuration software scans the PCI bus to determine what devices are actually present. The configuration software attempts to read a vendor identifier from each device; empty slots return the digital code FFFFh as an identifier. Valid vendor ID's cause the software to read other registers on the device, including device type. The configuration software then assigns a device number and writes resource allocations and an I/O base address to each of the devices, and loads device drivers into memory.
Automatic Power Management (APM) is a well-known technology for controlling power to various subsystems in a computer system. In 1996, the advanced configuration and power interface specification (ACPI) was introduced. Among other changes, the ACPI specification introduced operating system directed power management (OSPM). This operating system controlled power management within a computer and also replaced the basic input/output system (BIOS), as well as automatic power management (APM) application interfaces (API), and plug and play configuration processes. Both APM and ACPI use software to control power supplies to buses within the computer system, based on information obtained from devices on the various buses during a configuration phase upon power-up.
The ACPI specification includes four device power states: D3, D2, D1, and D0. Defined in terms of power consumption, device context. device driver, and the restore time, these device power states are not visible to the user. The device power state is recorded within the PCI configuration space for the device. In a D3 state, the operating system assumes the device has lost power. There is no requirement that hardware be provided to remove power from the device. In any case, in a D3 state, the device context has been lost, and so the operating system software has had to reinitialize the device when powering it back on. Since device context and power are lost, devices in this state have not decoded their address lines. Also, devices in the D3 state have the longest restore time.
A D2 state and a D1 state have also been defined for some classes of devices, as intermediate device power states. However, D2 and D1 state definitions have been class specific, and have not been defined across all devices. In the D0 device state, the device has been defined to be fully on, having the highest level of power consumption. The device in a D0 state has been completely activated and is responsive, retaining all relevant context.
The ACPI specification also includes four bus power states: B3, B2, B1, and B0. A bus in a B3 power state is without power, and cannot provide data, control signals, addresses, clock signals, or power supply signals to devices on the bus. A bus in a B0 state is completely operational, and transfers necessary signals among devices on the bus. Buses in the intermediate power states, i.e. power state B2 and power state B1, are defined by the bus manufacturer, but can be expected to provide less than fill bus functionality.
By moving power management into the operating system, ACPI has enabled operating system code to configure motherboard devices according to appropriate power management functions. This has been done while allowing software development of new operating systems independently of hardware development. ACPI has also allowed hardware to develop and ship under older ACPI compatible operating systems, while more current operating systems are under development. However, to provide operating system control over hardware, the operating system typically has polled hardware upon power-up to determine vendor identifier (ID), determine power requirements, and load appropriate drivers. Although the operating system can transition a configured device among various power states, neither the PCI loss of power management specification nor the ACPI specification allows for devices to be added to a system without rebooting the computer system.
SUMMARY OF THE INVENTION
Briefly, the present invention includes a computer system with an ACPI compliant PCI-to-PCI bridge which allows additional devices to be inserted, and allows existing devices to be removed or relocated without restarting the computer. A first PCI bus serves as a local bus, allowing a number of devices, including a PCI-to-PCI bridge, to be connected to the processor of a computer system The first PCI bus also provides power and a clock signal to the PCI-to-PCI bridge and to various other PCI devices located in slots on the bus. The PCI-to-PCI bridge allows expansion by coupling a second PCI bus to the first PCI bus, via the PCI-to-PCI bridge. The second PCI bus includes a number of PCI slots, one of which is coupled to the PCI-to-PCI bridge and receives clock and power signals from the PCI-to-PCI bridge. Other devices may be connected to the second PCI bus by inserting the additional devices into slots in the second PCI bus. Additional PCI buses may be connected to the first and second PCI buses by inserting additional PCI-to-PCI bridges into slots in the PCI buses.
According to the present invention, devices may be added without disabling the entire computer system or rebooting
Akin Gump Strauss Hauer & Feld & LLP
Beausoleil Robert
Campaq Computer Corporation
Phan Raymond N
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