Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-06-24
2001-05-22
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S649000, C438S655000, C438S666000, C438S785000, C257S750000, C257S754000, C257S768000, C257S770000
Reexamination Certificate
active
06235627
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having wirings or electrodes of metal silicide and a method for manufacturing the same.
Recently, the requirements for the high integration density and high speed operation of semiconductor devices are increased. In order to meet the requirements, the distance between elements and the element size are reduced and studies for lowering the resistance of internal wiring materials are made.
A lowering in the resistance is a serious subject in the word line of a memory device in which the RC delay significantly appears. Therefore, recently, in order to reduce the resistance of the word line, a polycide gate formed of a 2-layered structure having a polysilicon film and a metal silicide film is widely used. Since the resistance of a refractory metal silicide film is lower than that of the polysilicon film by approximately one order of magnitude, the refractory metal silicide film may be desirably used as a material of a low resistance wiring. As silicide, tungsten silicide (WSi
x
) is most widely used.
However, in order to cope with a fine wiring of 0.15 &mgr;m or less, it is required to further lower the resistance of the wiring so as to reduce the delay time. In order to realize the gate electrode having a low resistance of 1 &OHgr;/square or less by use of the polycide structure, silicide with a lower specific resistance is required.
As the low-resistance metal silicide, silicide of such as cobalt (Co) and nickel (Ni) is provided. However, since the halide of the above metals is low in the vapor pressure, it is extremely difficult to form the gate electrode by dry etching.
Therefore, when the above low-resistance metal silicide is used, the SALICIDE (Self Aligned Silicidation) technique is generally used. The technique is to deposit metal such as Co on the gate electrode and the source and drain regions and subject them to the heat treatment so as to selectively form silicide only on portions in which silicon is exposed. When the above technique is used, it is not necessary to subject the metal silicide to dry etching and it is possible to simultaneously form a silicide layer on the gate electrode and the source and drain regions.
On the other hand, with the progress of the miniaturization and high integration density, the requirement for the alignment precision of the exposure device becomes strict. Particularly, in a semiconductor memory as is represented by a DRAM, the integration density is high and the precision of alignment between the gate electrode and the contacts of the source or drain region is extremely severe.
Therefore, in order to solve the above problem, in the DRAM manufacturing process, the Self Aligned Contact (SAC) technique is used. The SAC technique is to surround the gate electrode with a silicon nitride film or the like and then form a contact hole by use of the high selectivity etching technique for a silicon oxide film against a silicon nitride film. By the SAC technique, even if the position of the contact is slightly deviated to the gate electrode side, the silicon nitride film is always present between the gate electrode and the contact, thereby preventing occurrence of an electrical short therebetween. Thus, the margin for the misalignment of the contact can be enhanced.
However, when the gate electrode is formed by use of the SALICIDE technique, it is impossible to previously cover the upper portion of the gate electrode with an insulating film for the sake of a step of forming metal silicide on the upper portion of the gate electrode. If the metal silicide is previously formed on the upper portion of the gate electrode and then an insulating film is formed on the metal silicide, formation of the contact hole cannot be effected in a self-alignment manner. That is, the SALICIDE technique and the Self Aligned Contact technique are incompatible. Therefore, it is extremely difficult to use the SALICIDE technique for a semiconductor device of high integration density such as a memory.
Moreover, if the low-resistance metal silicide of cobalt, nickel or the like is used for the gate electrode, it is extremely difficult to dry-etch the same into a desired shape. Therefore, it is considered to use the SALICIDE technique, but in this case, since it is incompatible with the Self Aligned Contact technique, it becomes extremely difficult to use the technique for the semiconductor device of high integration density.
BRIEF SUMMARY OF THE INVENTION
An object of this invention is to provide a semiconductor device in which a metal silicide material which is difficult to be subjected to dry etching can be used for the gate electrode, and at the same time, the Self Aligned Contact technique can be used and a method for manufacturing the same.
In order to attain the above object, a method for manufacturing a semiconductor device according to a first aspect of this invention comprises the steps of forming a groove portion whose side surface is formed of a first insulating film and whose bottom surface is formed of a silicon film on a main surface of a semiconductor substrate; forming a metal film on the silicon film of a bottom portion of the groove portion; reacting the silicon film and the metal film by a heat treatment to selectively form a metal silicide layer on the bottom portion of the groove portion; removing the metal film other than a portion thereof which has been converted to the metal silicide layer after the step of reacting the silicon film and the metal film; and forming a second insulating film on the metal silicide layer to form one of a wiring and an electrode which is covered with the first and the second insulating film.
A method for manufacturing a semiconductor device according to a second aspect of this invention comprises the steps of forming a groove portion whose side surface is formed of a first insulating film and whose bottom surface is formed of a silicon film and a third insulating film lying around the first insulating film on a main surface of a semiconductor substrate on which a gate insulating film is formed; forming a first metal film on the silicon film of the bottom portion of the groove portion; reacting the silicon film and the first metal film by a heat treatment to selectively form a first metal silicide layer on the bottom portion of the groove portion; removing the first metal film other than a portion which has been converted to the first metal silicide layer after the step of reacting the silicon film and the first metal film; forming a second insulating film on the first metal silicide layer to form one of a wiring and an electrode which is covered with the first and the second insulating film; forming a contact hole in the third insulating film in self-alignment with the first and the second insulating film; and filling a conductive material in the contact hole.
The step of forming the groove portion and the third insulating film may include the steps of forming the silicon film on the main surface of the semiconductor substrate on which a gate insulating film is formed; processing the silicon film into a desired pattern; forming the first insulating film on a side surface of the silicon film which has been processed into the desired pattern; forming the third insulating film on an entire portion of the main surface of the semiconductor substrate; making the third insulating film flat until an upper surface of the silicon film is exposed; and removing the silicon film by a preset thickness to form the groove portion surrounded by the first insulating film.
It is preferable to further include a step of making the silicon film flat between the step of forming the silicon film and the step of processing the silicon film into the desired pattern.
The step of forming the groove portion and the third insulating film may include the steps of forming the silicon film on the main surface of the semiconductor substrate on which a gate insulating film is formed; forming
Berry Renee R
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Nelms David
LandOfFree
Semiconductor device and method for manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2498798