Method of forming TEOS oxide films

Details Method of forming TEOS oxide films Method of forming TEOS oxide films

2000-06-28

2001-09-25

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S761000

Reexamination Certificate

active

06294484

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of forming TEOS oxide films for use as an interlayer insulating film. In particular, the invention is concerned with a method of controlling the thickness of one of the TEOS oxide films.
2. Description of the Related Art
There have been in use two kinds of TEOS (Tetra Ethyl Ortho Silicate) oxide films for an interlayer insulating film to be formed between metal patterns of a semiconductor device.
FIGS. 7A
to
7
C are sectional views showing a conventional method of forming the interlayer insulating film between the metal patterns of the semiconductor device.
With the conventional method, as shown in
FIG. 7A
, a metal pattern (made of W, Al, etc.)
202
is first formed on a semiconductor substrate
201
.
Subsequently, as shown in
FIG. 7B
, a plasma TEOS oxide film
203
having excellent coating property is formed on top of the metal pattern
202
.
The plasma TEOS oxide film is an oxide film formed by means of the plasma CVD method using, for example, an oxygen (O
2
) gas and a TEOS [Si(OC
2
H
5
)
4
] gas.
Thereafter, as shown in
FIG. 7C
, an O
3
-TEOS oxide film
204
having excellent self-flattening property is formed on top of the plasma TEOS oxide film
203
. The O
3
-TEOS oxide film is formed by means of the CVD method using an ozone (O
3
) gas and a TEOS gas.
However, a conventional structure wherein the plasma TEOS oxide film
203
is used at an underlayer has had a drawback in that the O
3
-TEOS oxide film
204
at an upper layer is prone to be affected by the substrate (after metal patterning), and consequently, becomes thinner in thickness than a target thickness.
Further, there has arisen another problem as a result of the thickness of the O
3
-TEOS oxide film
204
becoming thinner in that when forming a second metal pattern over the interlayer insulating film, there have occurred sites of the interlayer insulating film, in an undesirable step shape, that is, sites thereof in sectional shape at a very steep gradient, susceptible to formation of constricted parts, between the metal patterns, so that metal remnants are prone to be generated.
The invention has been developed to eliminate the problems described above, and an object of the invention is to provide a method of forming an interlayer insulating film of a semiconductor device, capable of preventing generation of metal remnants by rendering an upper layer of the interlayer insulating film thicker in thickness when forming an upper layer metal pattern over the interlayer insulating film.
SUMMARY OF THE INVENTION
To this end, in accordance with a first aspect of the invention, there is provided a method of forming an interlayer insulating film of a semiconductor device, wherein a plasma TEOS oxide film having a large intra-film electric charge is formed at an underlayer of the interlayer insulating film of the semiconductor device, and a O
3
-TEOS oxide film formed at an upper layer of the interlayer insulating film is rendered thicker in thickness.
In another aspect of the invention, change in a static charge within the plasma TEOS oxide film at the underlayer may be caused to occur by changing an output in a low frequency band of Rf with respect to the method of forming the interlayer insulating film of the semiconductor device.
With these features, change in the static charge within the plasma TEOS oxide film at the underlayer may be caused to occur by changing a ratio of a TEOS flow rate to an O
2
flow rate with respect to the method of forming the interlayer insulating film of the semiconductor device.


REFERENCES:
patent: 5560778 (1996-10-01), Park et al.
patent: 5605867 (1997-02-01), Sato et al.
patent: 5656337 (1997-08-01), Park et al.
patent: 6133160 (2000-10-01), Komiyama et al.
patent: 8-97285 (1996-04-01), None
patent: 9-64031 (1997-03-01), None

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