Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2000-06-09
2001-06-05
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S758000, C257S774000, C257S786000
Reexamination Certificate
active
06242813
ABSTRACT:
(1) TECHNICAL FIELD
This invention relates generally to a method for making integrated circuits and more particularly, the invention relates to methods that improve the bondability for deep-submicron integrated circuit package connections.
(2) DESCRIPTION OF THE PRIOR ART
The following three documents relate to methods dealing with the roughing of a surface to improve bondability.
U.S. Pat. No. 5,545,589 issued Aug. 13, 1996 to Y. Tomura et al., discloses a bump having a rugged side formed by an abrasive grinding process.
U.S. Pat. No. 5,487,999 issued Jan. 30, 1996 to W. Farnworth discloses a method for forming contacts on a semiconductor die. Each contact includes a rough textured surface having asperities adapted to penetrate the contact location on the die to a limited penetration depth. The height of the asperities is between 1000 A to 10,000 A. The textured surface and asperities are formed by etching a surface of a raised metal contact.
U.S. Pat. No. 5,461,008 issued Oct. 14, 1995 to R. Sutherland et al., discloses a method of suppressing adherence of silicon particles to IC bond pads, and corrosion thereof, during the dicing of silicon wafers by sawing. An anion of an organic acid is added to saw coolant water.
The packaging technologies that span the microelectronics industry from consumer electronics to low-end systems to high-performance systems are very diverse. The number of chips needed to form a system in the past increased from a few, in consumer electronics, to several thousands, in supercomputers. Given this, the packaging hierarchical technologies necessary to interconnect all these chips became complex; consumer electronics typically required a card or flexible-circuit carrier, and supercomputers required several boards, each containing several cards of multi-chip modules (MCMs).
Unpackaged or bare semiconductor dice are being increasingly used in the manufacture of electronic devices that employ MCM. These unpackaged dice are mounted directly to a substrate such as a printed circuit board. Although the MCM approach had been the technology of choice for the mainframes, its use in PCs is still emerging. A multichip approach seems the only practical choice when heterogeneous semiconductors are a necessity. Thus, there is a strong drive for dense, low cost interconnections capable of providing high degree of electromagnetic separation between the digital and RF signal and power interconnections. Yet another set of challenges stems from distributed computing (actually data processing) with its need for rapid and faultless transmission of enormously large data/information volumes.
Objectives of the electrical package design are to assure reliable and predictable signal transmission through the on-chip and off-chip interconnections. This is accomplished by numerous design considerations, all of which have to be met. Several of the key objectives are: To assure reliable functioning of the interchip signal interconnections (nets); to assure reliable on-chip nets performance; to optimize the packaging cross-sectional geometries and, if possible, materials; and to devise and verify “wiring rules”.
These objectives were pioneered by the developers of packaged electronics for the mainframes and supercomputers; now they are becoming increasingly pervasive for the entire range of digital processors, because their clock frequencies are going well beyond the 300 MHz range. The demand for higher performance had been driving down the overall dimensions of a computer while demanding more circuits and more bits of storage. The higher level of IC integration enables such size reductions, however, poor bondabilities are presently found on 0.35 um and 0.3 um packages.
SUMMARY OF THE INVENTION
Wirebonding has totally redeemed itself in reliability, manufacturability, and cost from where it was in the earliest era of semiconductor devices. It is still the dominant chip-connection technology in the semiconductor industry. Therefore, because the vast majority of all integrated circuit (IC) packages are assembled by wirebonding, it is important to understand this technology.
Wirebonding is popular as a result of continuous process improvement achieved through the development of sophisticated, automated equipment. Today's production lines can assemble the latest generation of packages with the evolutionary derivative of the welding technique used to manufacture the first transistor.
Today, hundreds of diverse plastic and ceramic packages utilize wirebonding. Despite this diversity, commonalities do exist. The wires are attached to the chip and package substrate, one at a time, using either a thermosonic or ultrasonic process. State of the art bonding technology produces two welds and a precisely shaped/routed wire loop in 100-125 ms, depending on the process used.
Most wirebonding processes combine either thermosonic (T/S) or ultrasonic (U/S) welding methods, with two different bonding methods for applying the wire to the chip and to the package surfaces. The two basic wirebonding techniques are ball bonding and wedge bonding. Approximately 93% of all semiconductor packages are manufactured using ball bonding method, while wedge bonding is used to produce about 5% percent of all assembled packages. A third method, thermocompression welding, may be used, but is not commonly used.
In ball bonding, wire is fed vertically, through a tool called a capillary. The wire is heated to a liquid state with an electronic spark discharge called an electronic flame-off (EFO). The surface tension of the molten metal forms a spherical shape, or ball, as the wire material solidifies, hence the process name “ball bonding”.
In accordance with the present invention, a method for forming a top metal layer to improve interconnect bondability for deep-submicron integrated circuit packages is provided.
A semiconductor integrated circuit structure includes a semiconductor substrate with deep-submicron electronic elements formed therein. The present invention is concerned with improvements to interface bonding between a top metal (Al Cu) layer of an integrated circuit structure and an interconnect wire. The improved bonding surface has an increased surface area with an enhanced surface profile for increasing a wire's mechanical bond and tensile strength.
Accordingly, it is an object of the present invention to provide a method for forming an improved interface structure for bonding an interconnect member to enhance electrical contact on a deep-submicron integrated circuit package.
It is another object of the present invention to increase the area of the bonding interface structure to improve its mechanical bond and tensile strength.
It is yet another object of the present invention to improve the surface profile of the bonding interface structure to further improve interconnect bondability.
It is yet another object of the present invention to provide a method for forming an improved interface structure for bonding an interconnect member that does not require additional cost or process steps.
It is an additional object of the present invention to provide the method useful in a semiconductor device having large scale integration.
Based on the intensive and thorough research and study by the present inventors, the above objects can be accomplished. In accordance with these aims and aspects, the present invention provides a method for processing and forming integrated circuits on a wafer which is to have an array of deep-submicron integrated circuit dice with improved bonding interfaces.
REFERENCES:
patent: 5461008 (1995-10-01), Sutherland et al.
patent: 5487999 (1996-01-01), Farnworth
patent: 5545589 (1996-08-01), Tomura et al.
patent: 5700735 (1997-12-01), Shiue et al.
patent: 5834365 (1998-11-01), Ming-Tsung et al.
patent: 5962919 (1999-10-01), Liang et al.
patent: 5963831 (1999-10-01), Fu
patent: 6110816 (2000-08-01), Huang et al.
patent: 7-39548 (1982-03-01), None
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patent: 3-19248 (1991-01-01), None
patent: 4-268737 (1992-09-01), None
patent: 6-53271 (1994-02-01),
Hsieh Han-Chang
Hsieh Hung-Chang
Huang Yung-Sheng
Ackerman Stephen B.
Chambliss Alonzo
Chaudhuri Olik
Saile George O.
Taiwan Semiconductor Manufacturing Company
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