Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-22
2001-06-19
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000
Reexamination Certificate
active
06249022
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for an integrated circuit device. More particularly, the present invention relates to a fabrication method for a flash memory cell.
2. Description of the Related Art
FIG. 1
is a schematic, cross-sectional view of a flash memory cell according to the prior art. Beside an oxide layer not being shown in the Figure, the conventional flash memory cell, as illustrated in
FIG. 1
, comprises a polysilicon gate
104
, a silicon nitride layer
102
, a source region
106
a
and a drain region
106
b,
wherein the source/drain region
106
a,
106
b
are formed near the two sides of the silicon nitride layer
102
in the substrate
100
.
There are two approaches for the above flash memory cell to perform the programming operation. One approach is to apply a positive voltage to the polysilicon gate
104
and a lesser positive voltage to the drain region
106
b.
Hot electrons are thus injected into and trapped in one end of the silicon nitride layer
102
near the drain region
106
b.
Another approach is to apply a positive voltage to the polysilicon gate
104
and a lesser positive voltage to the source region
106
a.
The hot electrons are injected onto and trapped in one end of the silicon nitride layer
102
near the source region
106
a.
One drawback of the conventional flash memory cell is that the hot electrons do not necessarily stay in the two ends of the silicon nitride layer
102
. These hot electrons sometimes redistribute themselves in the silicon nitride layer
102
. The occurrence of redistribution not only poses difficulties in the reading operation, it also leads to the serious problem of an over-erase.
SUMMARY OF THE INVENTION
Based on the foregoing, the current invention provides a fabrication method for a flash memory cell in which the problem of redistribution is prevented; the problem of over-erasure of a flash memory cell is also improved. The method of the present invention includes forming a shallow trench in a substrate, wherein the trench comprises a left sidewall and a right sidewall. A conformal oxide layer is then formed on the substrate. Thereafter, a first silicon nitride spacer is formed on the ultra thin oxide layer that covers the left sidewall of the shallow trench. Concurrently, a second silicon nitride spacer is formed on the ultra thin oxide layer that covers the right sidewall of the trench. A second oxide layer is then formed covering the first silicon nitride spacer and the second silicon nitride spacer. A polysilicon gate is further formed in the trench covering the second oxide layer. Subsequently, an ion implantation is conducted to form the source/drain region at the two sides of the gate in the substrate.
According to the preferred embodiment of the present invention, the second oxide layer is formed by growing an oxide layer on the first and the second silicon nitride spacers via a thermal oxidation process. The first oxide layer, which is not covered by the first and the second silicon nitride spacer, would becomes thicker. A second method of forming the second oxide layer includes deposition.
The first and the second silicon nitride spacers mentioned in the above are formed by forming a silicon nitride layer in the substrate and excessively filling the trench, followed by back-etching the silicon nitride layer using the substrate outside the trench as an etching end-point.
In other words, the present invention provides a two-bit flash memory cell, wherein the flash memory cell includes a substrate comprising a trench. The trench is sequentially filled with the following components. A conformal first oxide layer is formed on the trench, followed by forming silicon nitride spacers on the first oxide layer, which covers the sidewalls of the trench. A second oxide layer is then formed on the silicon nitride spacers, to sufficiently cover the silicon nitride spacers. A polysilicon gate, excessively filling the shallow trench, is formed on the second oxide layer, wherein a source/drain region is further formed on both sides of the polysilicon gate.
A special characteristic of the present invention is the formation of the silicon nitride spacers to cover the sidewalls of the shallow trench. Although, the conventional flash memory cell also comprises a silicon nitride layer, the present invention provides two isolated silicon nitride spacers for storing data, data of two bits can be stored by allocating four different levels of the reading current. In another words, a two-bit flash memory cell is provided. Furthermore, with two isolated silicon nitride spacers rather than a single silicon nitride layer, charge redistribution is less likely to occur in the flash memory cell. The problem of an over-erase can thereby be improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5429970 (1995-07-01), Hong
patent: 5606521 (1997-02-01), Kuo et al.
patent: 5675161 (1997-10-01), Thomas
patent: 5736765 (1998-04-01), Oh et al.
patent: 5877537 (1999-03-01), Aoki
patent: 6091102 (2000-07-01), Sekariapuram et al.
Lee Robin
Lin Chih-Hung
Loke Steven
Owens Douglas W.
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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