Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
1995-06-07
2001-08-21
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S206000
Reexamination Certificate
active
06279101
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a super-scaler microprocessor of the type which executes more than one instruction during each operating cycle of the microprocessor. The present invention more particularly relates to an instruction decoder for use in such a super-scalar microprocessor which is configured for decoding and dispatching a plurality of instructions to functional units for execution during each microprocessor operating cycle.
Scalar microprocessors are well known in the art. Such processors generally employ a pipelined architecture for obtaining and executing instructions in sequential stages including a fetch stage, a decode stage, an execute stage, and a write-back stage. When such a microprocessor continuously executes on instructions in consecutive operating cycles, during the fetch stage, a first instruction is fetched from a source of instructions, such as, for example, either an internal instruction cache or an external instruction memory. During the decode stage of the first instruction, the first instruction is decoded for, as an example, required read operands and the type of execution required by the instruction. During the decode stage of the first instruction, a second instruction enters the fetch stage and is fetched. During the execution stage of the first instruction, the first instruction is executed by the required functional unit while the second instruction advances to its decode stage and a third instruction enters its fetch stage. Lastly, during the write-back stage of the first instruction, the functional unit which executed the first instruction writes-back to memory the result of the execution. During the write-back stage of the first instruction, the second instruction advances to its execution stage, the third instruction advances to its decode stage, and a fourth instruction enters its fetch stage. As can thus be seen from the foregoing, a processor of this type can operate on as many as four instructions at a time and, given no traps or exception conditions, can execute at a rate up to one instruction execution per microprocessor operating cycle. Also, by virtue of the pipelined architecture, such processors are capable of performing a great number of complex operations per unit of time with a minimum of hardware.
Although such scalar processors have been commercially successful and proven reliable and capable of performance speeds suitable for many different applications, the concept of utilizing such a pipelined architecture in a processor for executing more than one instruction during each operating cycle has recently been introduced. In order to support the execution of a plurality of instructions during each operating cycle, such processors, known in the art as super-scalar processors, must be capable of fetching and decoding and dispatching to the functional units a plurality of instructions during each operating cycle. These functions must be carefully coordinated.
For example, program instruction order must be maintained to assure that instructions are dispatched to the functional units in the predicted order of execution. Dispatching instructions that are not in the predicted execution path would result in execution of instructions not intended to be executed. Also, if required operands are stored in a register file or a buffer, it must be assured that such operands are available for the required functional unit and that the required functional unit itself is available before the corresponding instruction is dispatched. Further, if one or more instructions of a previously fetched plurality of instructions cannot be dispatched, it is necessary to once again provide those instructions for decoding. This requires coordination between the instruction decoder and the source of instructions, such as, for example, an instruction cache. Still further, nonsequential branch instructions must also be accommodated. All of the foregoing places upon a super-scalar microprocessor extreme coordination requirements for the simultaneous fetching, decoding and dispatching, execution and write-back of multiple instructions at each stage.
The microprocessor of the present invention provides such coordination. It includes an instruction decoder embodying the present invention which maintains account of the availability of required operands, the availability of functional units, and the program instruction order. In addition, the interface between the instruction decoder and the instruction cache is elegant in its simplicity and operates in accordance with the same predefined protocol whether a plurality of instructions are newly presented to the instruction decoder, whether a previous plurality of instructions are once again presented to the instruction decoder, or whether a plurality of instructions presented to the instruction decoder contain a nonsequential branch instruction.
SUMMARY OF THE INVENTION
The present invention provides an instruction decoder for use in a processor of the type including a source of instructions and a plurality of functional units for executing the instructions, wherein the instruction decoder includes input means coupled to the source of instructions for receiving a block of instructions from the source of instructions. The block of instructions contains a plurality of the instructions. The instruction decoder further includes decoding means for decoding selected ones of the instructions of the received block of instructions. The decoding means also includes dispatch control means for applying a dispatch criteria to the selected ones of the instructions of the received block of instructions. The instruction decoder further includes output means coupled to the functional units and responsive to the dispatch control means for dispatching all of the selected instructions of the received block of instructions satisfying the dispatch criteria in parallel to the functional units.
The present invention further provides an instruction dispatch arrangement for use in a microprocessor of the type including multiple functional units and configured for executing a plurality of instructions during each microprocessor operating cycle. The instruction dispatch arrangement includes an instruction source for providing a block of instructions during each operating cycle wherein each block of instructions includes a plurality of instructions and wherein the instruction source also provides a predicted executed bit with selected ones of the instructions of the block of instructions. The arrangement further includes instruction decoder means coupled to the instruction source for applying a dispatch criteria to the selected instructions of the block of instructions and dispatching to the functional units for execution all the selected instructions satisfying the dispatch criteria.
The present invention still further provides a microprocessor arranged to execute at least one instruction during each cycle of consecutive operating cycles. The microprocessor includes instruction source means for providing a block of instructions during a present one of the operating cycles wherein the block of instructions includes a plurality of the instructions and wherein the instruction source means provides with each instruction a predicted executed bit which is set for selected ones of the instructions. The microprocessor further includes instruction decoder means coupled to the instruction source means for decoding and applying a dispatch criteria to the selected ones of the plurality of the instructions of the block of instructions during the present operating cycle and for dispatching during the next operating cycle immediately following the present operating cycle all the selected instructions satisfying the dispatch criteria and a plurality of functional units coupled to the instruction decoder means for receiving the dispatched instructions during the next operating cycle immediately following the present operating cycle for executing the dispatched instructions.
The invention still further provides an instruc
Johnson William M.
Witt David B.
Advanced Micro Devices , Inc.
Ellis Richard L.
Foley & Lardner
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