Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-03-07
2001-07-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06260175
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of integrated circuits and, more particularly, to the design of integrated circuits using predesigned and preverified core modules.
2. Description of the Related Art
In the past, integrated circuits were typically designed by defining the functionality of the integrated circuit as a whole and then designing from scratch the circuitry to implement the functionality. Computer aided design tools have long been employed to assist in the design of the transistor level circuitry. Upon definition of the transistor level circuitry, the mask layout of the integrated circuit is created.
Integrated circuits were often limited as to the number of transistors which could be employed therein. Accordingly, the amount of functionality included in a particular integrated circuit was rather limited. Therefore, it was relatively efficient to design each new integrated circuit individually from scratch, without directly leveraging off of the chip design of past work.
More recently, the number of transistors which are included upon a given integrated circuit has increased dramatically. Integrated circuits have thereby become more complex, integrating larger amounts of functionality as the number of transistors has grown. Since integrated circuits are increasing in complexity, the amount of time required to develop and fully test the new integrated circuit is increasing as well. At the same time, due to the pace of change in the semiconductor industry, the time-to-market for a product is required to be shorter.
Accordingly, it has become increasingly popular to design integrated circuits by selecting predesigned and preverified core modules for inclusion within the integrated circuit. Each core module performs a designated sub-function and is selected from a “library” of predefined and preverified core modules. The core modules can be used in conjunction with other core modules or custom logic to perform the overall functionality of the integrated circuit. Since each core module is predefined and preverified, the designer of the integrated circuit need not be concerned with the details of implementing the sub-function implemented by the core module. Instead, the designer includes the core module in the integrated circuit design and designs additional sub-functions for which a core is not available in custom logic. Time-to-market for the integrated circuit may thereby be decreased in comparison to the amount of time formerly required to design the functionality of the integrated circuit as a whole.
Although integrated circuit design techniques employing predefined core modules have been largely successful in accommodating expedient time-to-market, certain problems have emerged which hinder the expediency of the design, particularly in high-frequency applications. One such problem relates to minimizing clock skew between the predefined core modules and the custom logic. That is, while each of the predefined core modules are typically designed with internal clock distribution networks that are balanced, clock skew between various core modules and the custom logic may become problematic, particularly in high frequency applications. This problem occurs in part since the loading associated with the clock input of each core module may differ drastically among the core modules and may differ drastically from the loading presented by the clock input of the custom logic. Typically, substantial time and effort must be devoted to reducing clock skew between the core modules and the custom logic, and often extra logic such as phase locked loop circuits or data lock up latches must be employed. Accordingly, the integrated circuit may become larger in size, may become more difficult to test, and may be more complex to design. A method is desirable wherein an integrated circuit may be designed using predefined core modules integrated with custom logic wherein clock skew may be reduced without the requirement of additional phase lock loop circuits or lock up latches, and wherein overall design and test may be simplified.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a method for designing an integrated circuit including at least one predefined core module and a custom logic circuit in accordance with the invention whereby clock skew between the core module and the custom logic circuit may be reduced. In one embodiment, an integrated circuit designer selects core modules having desired functionality for inclusion within an integrated circuit. The core modules are selected from a library of core modules. Each core module in the library is predefined and pre-verified and may be provided as a synthesizeable register-transfer level (RTL) description which can be synthesized along with RTL descriptions of other logic blocks in the integrated circuit. Alternatively, each core module may be provided as a pre-laidout integrated circuit mask which can be included in the final integrated circuit mask design. Upon selection of appropriate core modules, the designer defines a custom logic circuit for integration with the core modules. Each core module is advantageously provided with multiple clock inputs, each having a relatively low fan-out of associated clocked elements. In one embodiment, the fan-out associated with each clock input of a core module is limited to eight. Since the fan-out associated with each clock input is selectively low, each clock input may be connected to form a leaf-level component of a chip-level balanced clock tree (BCT) clock distribution structure associated with the integrated circuit as a whole. Accordingly, the core module timing can be balanced with the chip level timing in a simpler manner, with more precision, and without the requirement of additional phase locked loop circuits or data lock up latches. Thus, clock skew between the core modules and the custom logic may be reduced. Clock network fan-out and clock buffers associated with the core modules can be matched to those of the custom logic circuit. Additionally, pairs of (or multiples of) core module clock inputs can be joined together to match custom logic designs which use larger fan-outs, for example 16, at the leaf level. Furthermore, for designs wherein the custom logic circuit fan-out is between that of the core module fan-out and an integer multiple thereof, clock matching can be achieved by using load balancing cells, buffer re-sizing, or by placing “dummy” loads implemented in the custom logic circuit on the same net as the core module clock input.
A method of designing an integrated circuit in accordance with the present invention may advantageously allow expedient and inexpensive integrated circuit design, test, and manufacture when predefined and preverified core modules are integrated with custom logic circuitry. Clock skew between the core modules and the custom logic may be reduced, and the “drop in” attributes of the core module design methodology may be enhanced. Finally, extra logic such as phase lock loops or data lock up latches may not be required and the manual work of designing and analyzing these elements may be eliminated. This may allow for smaller designs and the ability to operate at higher frequencies. Furthermore, no new timing analysis associated with the core module may be required.
Broadly speaking, the present invention contemplates a method of designing an integrated circuit including at least one predefined and preverified core module and a custom logic circuit whereby clock skew between the core module and the custom logic circuit may be reduced. The method comprises predefining the core module with a first plurality of clock inputs, wherein each of the clock inputs of the core module is coupled to a given number of clocked elements of the core module, and selecting the core module for incorporation within the integrated circuit. The method further comprises defining the custom logic circuit with a second plurality of clock inputs, and coupling each of the clock inputs of the co
Conley Rose & Tayon
LSI Logic Corporation
Siek Vuthe
Smith Matthew
LandOfFree
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