Multiple finger polysilicon gate structure and method of making

Details Multiple finger polysilicon gate structure and method of making Multiple finger polysilicon gate structure and method of making

1998-08-12

2001-03-06

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S762000, C438S697000

Reexamination Certificate

active

06197671

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to MOS transistors and methods for fabricating the transistors. More particularly, the invention relates to MOS transistors having multiple finger gate structures and capable of operating at high frequencies.
2. Description of the Related Art
High frequency wireless MOS technology for gate lengths below 0.5&mgr; is an emerging technology. Devices having gate lengths of 0.3&mgr; and 0.1&mgr; with intrinsic cut-off frequencies f
t
as high as 10 GHz and 60 GHz, respectively, have been reported in the literature.
Two device characteristics are particularly important for high frequency wireless MOS transistors. The intrinsic cut off frequency, f
t
, can be represented as:
f
t
=g
m
/[2&pgr;(
C
gs
+C
gd
)],
where g
m
=transconductance of the MOS transistor, C
gs
=signal gate-to-source capacitance, C
gd
=signal gate-to-drain capacitance.
Another important variable for high frequency transistors is f
max
, the maximum frequency of oscillation (the frequency at which a device can amplify the power of a signal). Maximum frequency, f
max
, is defined as:
f
max
=f
t
/2[2&pgr;
f
t
C
gd
+g
o
(
R
g
+R
s
)]
½
,
where g
o
=output conductance, R
g
=total gate resistance and R
s
=source resistance.
For a given CMOS technology, based on these relationships, the only way to increase f
max
is to make the term [2&pgr;f
t
C
gd
+g
o
(R
g
+R
s
)] less than 1. From this relationship, it can be seen that reducing C
gs
and C
gd
(overlap of drain and source regions under the gate) is desirable. However, conventional MOS technology uses “Light-Doped Drain” (LDD) technology to minimize adverse effects of hot carriers on device reliability, leading to typical values of C
gs
+C
gd
in the range of 60 fF for 0.35&mgr;-0.5&mgr; technologies.
Thus, the only option is to minimize the total gate resistance R
g
.
FIG. 1
graphically represents f
max
calculated as a function of R
g
. Until R
g
is less than 100 &OHgr;, f
max
is smaller than f
t
, being limited by R
g
. For a 0.35&mgr; gate with resistivity of 30 &OHgr;/sq, a total gate width W of 20&mgr; will lead to R
g
=1700 &OHgr;!
Most FETs used in a CMOS VLSI chip have a straight gate electrode and rectangular source and drain diffused areas on either side of the gate. The source and drain areas are contacted by metal conductors at many locations along the device width. Other FET configurations are known. For example, the literature reports a wide FET in which the gate appears to be in a serpentine pattern and is “driven” only from one end. There is no shorting of the entire gate area.
It is therefore desirable to provide MOS transistors with reduced gate resistance and drain/source-to-gate overlap capacitance.
SUMMARY OF THE INVENTION
The present invention addresses these and other problems by using a new structure having reduced total gate resistance and drain/source-to-gate overlap capacitance, thereby increasing f
max
and to some extent f
t
, respectively. Generally, this structure is a transistor having a polysilicon gate that is totally shorted by a metal such as aluminum. As a result, transistors according to the present invention are especially suitable for high frequency wireless MOS technologies where gates lengths are less than 0.5&mgr;.
In one embodiment, MOS transistors according to the present invention include a polysilicon gate underlying a metal interconnect. The interconnect is formed from a first metal layer and a second metal layer. The first metal layer is formed over the gate. The second metal layer is formed on the first metal layer. Together, the first and second metal layers form a stack that completely shorts the gate. In a preferred embodiment, the polysilicon gate has several fingers joined in a serpentine pattern and separated by oxide-filled spaces. More preferably, the fingers have a thickness k and the oxide-filled spaces have a width of ≦2k and are formed from a conformal oxide layer having a thickness of k.
The present invention is also directed to new processes for fabricating MOS transistors having this gate structure.
In one embodiment of the method, a first step defines a polysilicon gate having a plurality of fingers in a serpentine pattern and separated by spaces. Then, a conformal oxide is deposited over the fingers and in the spaces. An anisotropic etch of the conformal oxide follows with endpoint detection on the polysilicon to produce a planarized profile of the fingers and oxide-filled spaces. Next, a first metal layer is formed on the planarized profile and a second metal layer is formed on the first metal layer to form an interconnect that shorts the polysilicon fingers at the same time.
In a preferred embodiment, a series of specially designed masks is used to form features in the desired configuration at each level of the transistor. A first mask is used to define a gate area in an active device area surrounded by field oxide regions on a substrate. A polysilicon layer is patterned and etched through a second mask to form a polysilicon gate of thickness k, having a plurality of fingers joined in a serpentine pattern and separated by spaces of width less than or equal to 2k.
The second mask defines first, second, third and fourth regions: the first region defining where the fingers are formed from the polysilicon layer, the second region defining where the polysilicon is etched, but field oxide remains, the third region defining where the polysilicon is etched between the fingers to form the spaces, and the fourth region defining where the polysilicon is etched to open contact windows. Oxide is formed along the periphery of the polysilicon in the fourth regions.
A metal layer of refractory metal silicide or doped polysilicon deposited on the fingers and oxide-filled spaces is etched using a third mask so that the first metal layer covers the active device area but does not cover any contact openings. An interlevel dielectric layer is contact mask printed and etched using a fourth mask to expose the first metal layer.
Finally, an aluminum layer is deposited and etched to form an interconnect with the first metal layer and to form source and drain contacts using a fifth mask, the interconnect serving to short the polysilicon fingers at the same time.


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* S.P. Voinigescu et al., “An Assessment of the State-of-the-Art 0.5 &mgr;m Bulk CMOS Technology for RF Applications”, IEDM 95, pp. 721-724.
* H. Nakamura et al., “A Novel Sense Amplifier for Flexible Voltage Operation NAND Flash Memories”, 1995 Symposium on VLSI Circuits Digest of Technical Papers, pp. 71-72.
* T. Tanzawa et al., “A Stable Programming Pulse Generator for High-Speed Programming Single Power Supply Voltage Flash Memories”, 1995 Symposium on VLSI Circuits Digest of Technical Papers, pp. 73-74.

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