Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-09-24
2001-03-27
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S155000, C349S042000, C349S043000
Reexamination Certificate
active
06207480
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for manufacturing a thin film transistor (TFT) array panel for a liquid crystal display (LCD).
(b) Description of the Related Art
Thin film transistors used for an LCD have two different types of structure. One is an etch-back type and the other is an etch-stopper type.
When manufacturing an etch-back type TFT, an amorphous silicon layer and a doped amorphous silicon layer are deposited in sequence and patterned. Next, a metal layer is deposited and patterned to form a data wire including source and drain electrodes, and the doped amorphous silicon layer is etched by using the source and the drain electrodes as etching mask. In the etch stopper type TFT, an etch stopper, which has a large etch selectivity, is formed between an amorphous silicon layer and a doped amorphous silicon layer.
Now, a conventional method for manufacturing a TFT array panel for an LCD will be described with reference to the
FIGS. 1A
to
1
D.
FIGS. 1A
to
1
D are cross-sectional views of a TFT array panel, as it undergoes sequential processing steps according to the conventional manufacturing method.
First, as shown in
FIG. 1A
, an aluminum-neodymium (Al—Nd) layer
11
and a molybdenum (Mo) layer
12
are sequentially deposited on a substrate
1
and patterned to form a gate electrode
10
. That is, a gate wire having the gate electrode
10
is formed. A gate insulating layer
13
, an amorphous silicon layer
14
and an n+ amorphous silicon layer
15
are sequentially deposited over the gate electrode
10
.
Next, as shown in
FIG. 1B
, the amorphous silicon layer
14
and the n+ amorphous silicon layer
15
are patterned to form a semiconductor pattern. Subsequently, with reference to
FIG. 1C
, a metal layer is deposited on the n+ amorphous silicon layer
15
and patterned to form a source electrode
16
and a drain electrode
17
. Before the deposition of the metal layer, a natural oxide layer (not shown) formed on the n+ amorphous silicon layer
15
is removed by a wet etch cleaning process using hydrogen fluoride (HF). Accordingly, the contact resistance between the n+ amorphous silicon layer
15
and both the source electrode
16
and the drain electrode
17
is reduced. After forming the source electrode
16
and the drain electrode
17
, an exposed portion of the n+ amorphous silicon layer
15
is etched using the source and drain electrode
16
and
17
as mask.
As shown in
FIG. 1D
, a passivation layer
18
is deposited and patterned to have a contact hole
19
exposing the drain electrode
17
. Finally, an indium tin oxide (ITO) layer is deposited and patterned to form a pixel electrode
20
.
However, the conventional method for manufacturing a TFT array panel has many problems.
Impurities, which are generated during semiconductor patterning and HF cleaning processes, may remain on the n+ amorphous silicon layer
15
, and cause disconnections of the source electrode
16
and the drain electrode
17
. Further, even with HF cleaning, portions of the natural oxide layer remain. The remaining natural oxide coupled with the impurities, degrades an ohmic contact between the n+ amorphous silicon layer
15
and both the source electrode
16
and the drain electrode
17
, thereby reducing the on current (Ion) of the TFT. Furthermore, pixel electrodes
20
adjacent to a data line (not shown) interposed therebetween, may be short-circuited when forming the pixel electrodes
20
due to the ITO residues between the pixel electrodes
20
. Finally, a photomask misalignment occurring in the photolithography process of forming the amorphous silicon layer
14
may result in stitch defects because the parasitic electrostatic capacitance (Cgd) between the gate electrode
10
and the drain electrode
17
becomes different depending on each photo shot.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to prevent disconnections of a source electrode and a drain electrode.
It is another object of the present invention to improve an ohmic contact between a semiconductor layer and both a source electrode and a drain electrode.
It is still another object of the present invention to prevent short-circuit between the adjacent pixel electrodes.
It is still yet another object of the present invention to reduce stitch defects.
These and other objects are achieved, according to the present invention, by the following process. After a gate wire is formed, a gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a data metal layer are sequentially deposited in vacuum. The data metal layer is patterned to form a data wire. Next, a doped amorphous silicon layer and an amorphous silicon layer are patterned.
In more detail, a TFT array panel is manufactured by a method including following processes. A gate wire is formed on an insulating substrate, then a gate insulating layer, an amorphous silicon layer and a metal layer are sequentially deposited. The metal layer is patterned to form a data line, a source electrode and a drain electrode, and the amorphous silicon layer is also patterned. A passivation layer having a contact hole, which exposes a part of the drain electrode, is formed. Finally, a pixel electrode, which is connected to the drain electrode through the contact hole, is formed.
It is preferable that the sequence deposition of the gate insulating layer, the amorphous silicon layer and the metal layer is performed in a vacuum state.
It is possible to deposit a doped amorphous silicon layer after the deposition of the amorphous silicon layer in the sequential deposition process of the amorphous silicon layer and the metal layer, the doped amorphous silicon layer also being patterned when patterning the amorphous silicon layer. After patterning the amorphous silicon layer, the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper.
It is also possible to include the deposition of the doped amorphous silicon layer after the deposition of the amorphous silicon layer in the sequential deposition process of the amorphous silicon layer and the metal layer. After patterning the data line, the source electrode and the drain electrode, the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. It is preferable that the gate insulating layer, the amorphous silicon layer, the doped amorphous silicon layer and the metal layer are sequentially deposited in vacuum. An equipment that has integrated a sputter equipment and a chemical vapor deposition (CVD) equipment is used for this purpose.
The amorphous silicon layer may be patterned as follows. A photoresist pattern is formed through coating, exposure and development to have a width of 0.1 to 0.4 &mgr;m wider than the source electrode and the drain electrode but have the same width as or narrower than the data line. Next, the amorphous silicon layer is overetched to make a groove with a depth of 0.1 to 0.4 &mgr;m under the data line.
The gate wire may be a single layer and made of one of Al, an Al alloy, Mo, a Mo alloy, Cr, a Cr alloy, Ta and a Ta alloy, or double-layered and made of any two of the above described materials.
REFERENCES:
patent: 5528082 (1996-06-01), Ho et al.
patent: 5614055 (1997-03-01), Fairbairn et al.
patent: 5739877 (1998-04-01), Onisawa et al.
patent: 6019796 (2000-02-01), Mei et al.
Cha Jong-Hwan
Jang Geun-ha
Yi Dae-Sung
Elms Richard
Howrey Simon Arnold & White , LLP
Samsung Electronics Co., Inc.
Wilson Christian D.
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