Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-01-21
2001-03-27
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06209118
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to application specific integrated circuits (ASICs). More particularly, the present invention relates to a method for constructing a standard cell ASIC and a structure for a standard cell ASIC that speeds metal mask changes and permits logic changes by programming configuration bits.
2. Description of the Prior Art
Integrated circuits are increasingly complex and the demands of technology cause the designs to be updated or changed constantly. Errors can be made and designs can almost always be improved. It is desirable that design changes be implemented with a minimal redesign of the chip. A fundamental redesign may take weeks and be followed by many days in which the multiple steps for manufacture of the newly-designed chips must be executed.
In traditional standard cell ASICs, the chip designers may add spare logic gates for use in making design modifications when testing reveals problems. These modifications are often effected by defining changes in the metal mask to make a new metal mask. Metal mask changes can speed the turnaround time for modifications, because the base layer masks need not be changed and modified chips can be fabricated from previously-made dies completed only to the stage before the first metal layer is placed (“metal one stage”). The spare logic gates are connected by the new metal mask and problems found in checkout testing can be corrected quickly.
Normally, the spare gates have their inputs tied low or high until they are used in a metal mask change. When the spare gates must be used to form a complex logic function, many of the spare gates must be connected together. The design of the connections needed to implement the desired complex logic function from a group of spare gates may involve considerable time and effort by the logic designer and layout editor in creating a new metal mask.
For some chips, connection changes can be made by focussed ion beam processing. To the extent a focussed ion beam method is used for connecting up spare gates on chips, this method is expensive and effective for short connection paths only. The probability of a defect increases with the length of connection and the number of connections. Additionally, each chip modified must be processed individually.
Field programmable gate arrays (FPGAs) have been used in some applications to permit quick turn-around time with no Non-recurring engineering (NRE) cost, but at a high per chip cost (in some cases, in the hundreds of dollars). In anti-fuse type FPGAs, certain gate arrays are programmable by placing the chip in a special device that burns out certain connections. In SRAM type FPGAs, the programming information is written into an SRAM that is used to enable the extra gates. However, FPGAs of either type are relatively expensive, often slow and may not be able to implement many logic functions. In addition, each FPGA to be programmed must be handled individually.
Thus, there exists a need for a more effective approach for designing a standard cell ASIC capable of being logically modified.
SUMMARY OF THE INVENTION
An application specific integrated circuit has at least one standard cell, integrated circuit connection circuitry connected to the at least one standard cell and at least one programmable circuit that is selectively connectable to the integrated circuit connection circuitry. The connection is made by metal mask changes. The programmable circuit is a general-purpose logic block.
The invention also encompasses a method for modifying the logic of an application specific integrated circuit having integrated circuit connection circuitry comprising:
(a) placing at least one programmable circuit on a die before the metal one stage;
(b) if logic modifications are needed, then connecting the at least one programmable circuit to the integrated circuit connection circuitry in the metal one stage such that the design modifications may be implemented; and
(c) configuring the at least one programmable circuit such that the design modifications may be implemented.
REFERENCES:
patent: Re. 34363 (1993-08-01), Freeman
patent: 5089973 (1992-02-01), Furtek
patent: 5122685 (1992-06-01), Chan et al.
patent: 5220213 (1993-06-01), Chan et al.
patent: 5338983 (1994-08-01), Agarwala
patent: 5416367 (1995-05-01), Chan et al.
patent: 5477167 (1995-12-01), Chua
patent: 5587669 (1996-12-01), Chan et al.
patent: 5594364 (1997-01-01), Chan et al.
patent: 5732246 (1998-03-01), Gould et al.
patent: 5745734 (1998-04-01), Craft et al.
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5859543 (1999-01-01), Kolze
patent: 5943488 (1999-08-01), Raza
Gokhale et al. “The Logic Description Generator,” 1990 Proceedings of the International Conference on Application Specific Array Processors, Sep. 5-7, 1990, pp. 111-120.*
Sait et al. “Designing ASICs with UAHPL,” IEEE Circuits and Devices Magazine, Mar. 1995, vol. 11, Issue 2, pp. 14-24.*
Wiiliams “Programmable Logic Arrays for Prototype Computer Implemetation,” IEE Colloquium on Programmable Logic Devices for Digital Systems Implemenation, pp. 5/1-5/3, 1990.*
Salcic and Maunder SimP: A Core for FPLD-Based Custom-Configurable Processors, 2nd International Conference on ASIC, Oct. 21-24, 1996 pp. 197-201.*
Lees et al. “A REconfigurable Parallel Inference Processor for High Speed Fuzzy Systems,” 1996 IEEE International Symposium on Circuits and Systems, May 12-15, 1996, p. 539-542 vol. 3.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Siek Vuthe
Smith Matthew
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