Electrical computers and digital processing systems: processing – Processing control
Reexamination Certificate
1998-12-16
2001-07-24
Hjerpe, Richard (Department: 2674)
Electrical computers and digital processing systems: processing
Processing control
C712S210000, C712S218000, C712S244000, C712S205000
Reexamination Certificate
active
06266768
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to the execution of out-of-order load instructions in a processor.
BACKGROUND INFORMATION
In order to increase the operating speed of microprocessors, architectures have been designed and implemented that allow for the out-of-order execution of instructions within the microprocessor. An advantage of out-of-order execution of instructions is that it allows load miss latencies to be hidden while useful work is being performed. However, traditionally, load and store instructions have not been executed out of order because of the very nature of their purpose.
Generally, it is architecturally impermissible for a load instruction, which is subsequent in program order to a previous load instruction to return “older” data, which can occur if load instructions are permitted to be executed out of order. Nevertheless, techniques have been implemented to attempt to execute load instructions out of order. However, such techniques have often required too many processor cycles to execute. As microprocessor speeds continually increase, there is a need in the art for an ability to execute in parallel such load instructions and to correct for such problems as described above in a more efficient and faster manner.
SUMMARY OF THE INVENTION
The present invention provides a mechanism to allow out-of-order load execution and a means to recover from problems which occur from such execution in an efficient manner. For example, one problem occurs when a snoop invalidate for the associated cache line occurs between execution of the two load instructions. Herein, a snoop invalidate means a signal received from the memory hierarchy indicating that another bus device (e.g. another processor) has obtained ownership of the cache line.
The present invention addresses the foregoing need by tagging load and store instructions and then maintaining entries in separate queues for the load and store instructions, in conformance with the assigned tags.
At instruction dispatch, each load instruction is assigned an LTAG (load tag), where the LTAG is incremented by a preceding load instruction (in program order). Addresses are queued in a load reorder queue in position relative to their LTAG. Conflicts can then be detected since the relative program order is known at address generation time.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 5247628 (1993-09-01), Grohoski
patent: 5619662 (1997-04-01), Steely, Jr. et al.
patent: 5931957 (2000-08-01), Konigsburg et al.
Frederick, Jr. Marlin Wayne
Ronchetti Bruce Joseph
Thatcher Larry Edward
England Anthony V. S.
Hjerpe Richard
International Business Machines - Corporation
Kordzik Kelly K.
Monestime Mackly
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