Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-06
2001-08-14
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S319000, C257S316000, C257S315000
Reexamination Certificate
active
06274907
ABSTRACT:
This application is based on Japanese patent application No. HEI 11-167750, filed on Jun. 15, 1999, all the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device capable of reading, writing and erasing data and its manufacture method using SOI (silicon on insulator), SIMOX (separation by implanted oxygen) and the like.
Because of ultra fine patterns and a rapid increase in the memory capacity, nonvolatile semiconductor memories such as flash memories and EEPROMs are expected to be used as alternatives of hard disks widely used as storage devices, and some of then are actually used as such alternatives. If flash memories, EEPROMs or the like can be integrated highly to provide a large memory capacity sufficient for the alternatives of hard disks, many advantages are expected. Namely, products using such memories are resistant to vibrations because mechanical components are not used, and have a low power consumption which is suitable for a battery operation of the products, particularly for various types of portable digital equipments. New techniques allowing a much higher integration and larger capacity have been long desired.
b) Description of the Related Art
A field oxide film as an element separation region of a flash memory, EEPROM or the like is formed on a semiconductor substrate to a thickness of 400 nm to 800 nm by local oxidation of silicon (LOCOS).
On the substrate formed with element separation regions through LOCOS, a first gate dielectric film, a floating gate (polysilicon), a second gate dielectric film, and a control gate (polysilicon) are sequentially laminated to form the memory cell structure of a nonvolatile memory. The control gate extends in a direction (column direction) crossing the element separation region to form a word line of the nonvolatile semiconductor memory.
A common source wiring line running in parallel with the word line is formed by selectively removing the LOCOS oxide film between adjacent two control gates and implanting arsenic or the like into the p-type semiconductor substrate under the conditions of, for example, a dose of 3×10
15
cm
−2
and an acceleration energy of 60 keV. Source regions (each being generally formed between adjacent two control gates) formed in the semiconductor substrate on one side of the floating gate are electrically connected in the column direction by the impurity doped regions to form the common source region.
The nonvolatile semiconductor memory device described above has, however, an element separation width limit and is not suitable for ultra fine patterning because LOCOS is used for element separations.
This problem also occurs when a hybrid nonvolatile semiconductor memory device is formed having a logic circuit and a nonvolatile semiconductor memory device formed on the same substrate.
It is essential to make fine transistors in order to speed up the operation of a logic circuit. As a transistor is made fine (e.g., a short gate length), it is necessary to shallow the depth of the source/drain regions. In order to retain a certain degree of a current capacity, the doping concentration of the source/drain regions is required to be set high.
In this case, parasitic capacitance increases and hinders the high speed operation of a nonvolatile semiconductor memory device.
Instead of forming the common source region by etching the element separation region through self-alignment using the control gates (actually, side wall spacers formed on the side walls of the control gates) as a mask, a nitride film patterned by using photoresist may be used as an etching mask. In this case, the edge of the resist pattern is rounded and so the edge of the nitride film is rounded. Therefore, there is a variation in the etching amounts of the element separation region so that memory cells of the nonvolatile memory device have a variation in their characteristics.
Further, since adjacent source regions are connected only by regions (doped layers) formed by implanting arsenic or the like into the p-type semiconductor substrate, the sheet resistance of the common source region is high. With a high sheet resistance, a voltage dropped by this resistance becomes high. Therefore, when data stored in the memory device is erased, a variation in the accumulated charge amounts in the floating gates of a plurality of memory cells becomes large.
SUMMARY OF THE INVENTION.
It is an object of the present invention to provide a high performance nonvolatile semiconductor memory device capable of a high speed operation and a high integration.
According to one aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a semiconductor substrate; an underlying dielectric layer formed on the semiconductor substrate; a plurality of first conductivity type striped-shape semiconductor layers formed on the underlying dielectric layer and disposed apart from each other in a row direction; a trench formed between each pair of adjacent first conductivity type semiconductor layers and extending in the row direction; a plurality of buried dielectric portions filled with a separation dielectric layer and formed discontinuously in the row direction in each of the trenches and aligned in a column direction; an opening formed in the underlying dielectric layer between the buried dielectric portions adjacent in the column direction; at least a first gate dielectric film formed on each of the first conductivity type semiconductor layers, a plurality of floating gates each formed on each of the first gate dielectric films and all separated in the column direction on the buried dielectric portions, a second gate dielectric film formed on each of the floating gates, and a plurality of control gates formed on the second gate dielectric films and extending in same column directions as the plurality of floating gates; a source region of a second conductivity type formed in the first conductivity type semiconductor layer between the openings adjacent in the column direction on one side of each of the floating gates; a drain region of a second conductivity type formed in the first conductivity type semiconductor layer between the buried dielectric portions adjacent in the column direction on the other side of each of the floating gates; a source region connecting semiconductor layer of the second conductivity type being continuous with the source region and formed at least on the semiconductor substrate in the trench formed in the opening between the source regions in the column direction; and a conductive film formed on the source region connecting semiconductor layers and the source regions and extending in the column direction.
According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device comprising the steps separating a first conductivity type semiconductor layer formed on a semiconductor substrate having a buried dielectric layer on a front surface side of the semiconductor substrate, by forming a plurality of trenches elongated in a row direction; filling a dielectric layer in the trench; forming a first gate dielectric film at least on the first conductivity type semiconductor layer; forming a first conductive polysilicon layer on the substrate formed with the first gate dielectric film; removing the first polysilicon layer to leave islands disposed apart from each other in the row direction; forming a second gate dielectric film at least on a surface of the first polysilicon layer; forming a second polysilicon layer on the second gate dielectric film; etching at least the second polysilicon layer, the second gate dielectric layer and the first polysilicon layer in a striped-shape in a column direction to form a stacked-layer structure including the second polysilicon layer, the second gate dielectric layer and the first polysilicon layer; forming source and drain regions in the first conductivity typ
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Loke Steven
Owens Douglas W.
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