Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-06-30
2001-05-08
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S517000, C438S404000, C438S430000
Reexamination Certificate
active
06228691
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor process and, more particularly, relates to a silicon-on-insulator device and a process of producing controllable thickness for a silicon layer of a silicon-on-insulator (SOI) device.
BACKGROUND
Silicon-on-insulator (SOI) substrates have recently become desirable for many technologies, including extreme scaling of metal-oxide semiconductor (MOS) and complementary metal-oxide semiconductor (CMOS) devices, advanced MOS junction-type field-effect transistors (MOSFETs), and quantum wires and dots. This is primarily because SOI fabrication processes result in increased packing densities, improved performances, better device isolations and reduced extrinsic parasitic elements, particularly those of the source and drain as well as leakage currents and thus significantly speeding up circuit operations.
As the name implies, SOI substrates generally comprise a thin layer of silicon on top of an insulator, wherein circuit components are formed in and on the thin layer of silicon. The insulator can be silicon oxide (SO
2
), sapphire, or any appropriate material. For example, a sapphire substrate may be used as an insulator for target radio-frequency (RF) applications. In contrast, a bulk silicon wafer with an oxide layer as the substrate may be used as an insulator for target digital logic applications. In both cases, the insulator may serve to reduce junction capacitance between the heavily-doped devices and the lightly-doped bulk substrate which may translate to less power consumption and greater circuit speed.
SOI substrate may be fully-deleted in which a depletion region of an entire channel is fully active, or may be partially-depleted in which the depletion region of the channel is not fully active. In both partially or fully depleted devices, the silicon layer may be thinner than the depletion region. However, fully-depleted SOI substrates have rarely been used in the fabrication of SOI MOSFETs, for example. This is because the uniform thickness control of the silicon layer of a SOI substrate on which the channel is formed for fully-depleted SOI substrates has been exceedingly difficult. Variation in the thickness of the silicon layer can severely impact the threshold voltage of each transistor on the SOI substrate. Consequently, partially-depleted (PD) SOI substrates have widely been used instead.
Currently, there are several techniques available for the fabrication of SOI substrates. An established technique for fabricating SOI substrates is known as “separation by implantation of oxygen” (SIMOX), where oxygen is implanted below the silicon surface and the substrate is annealed to provide a buried silicon oxide layer with a silicon overlayer. The implantation time can be intensive and cost prohibitive. Moreover, the SOI substrate may be exposed to high surface damage and contamination. A second technique is known as “bond-and-etch-back” SOI (BESOI), where an oxidized wafer is first diffusion-bonded to an unoxidized wafer, and the backside of the oxidized wafer is then grinded, polished, and etched to the desired device layer. The BESOI approach may be free from the implant damage inherent in the SIMOX approach. However, time consuming sequence of grinding, polishing, and etching may be required. Another technique is known as the hydrogen implantation and separation approach (also called Smart-Cut®), where hydrogen is implanted into silicon with a thermally grown oxide to form embrittlement of the silicon substrate underneath the oxide layer. The implanted wafer may then be bonded with another silicon wafer with an oxide overlayer. The bonded wafer may be “cut” across the wafer at the peak location of the hydrogen implant by appropriate annealing. These fabrication techniques may not be suitable for fabricating fully-depleted SOI substrates, since the uniform thickness of the silicon layer of a SOI substrate may be difficult to achieve.
More complex techniques for fabricating filly-depleted SOI devices include the selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) technique as described in “
SOI
-
MOSFET Structures Using Silicon Selective
(
SEG
)
and Epitaxial Lateral Overgrowth
(
ELO
)” by Gerold W. Neudeck, submitted to Semiconductor Research Corporation, May 1997, and the combination of BESOI and Smart-Cut® as described in “Ultra-Cut: A Simple Technique For The Fabrication Of SOI Substrates With Ultra-Thin (<5 nm) Silicon Films” by K. D. Hobart et al., Naval Research Laboratory, published by the IEEE International SOI Conference Proceedings, October 1998. However, none of these techniques appears to be simple, cost-effective, and efficient for fabricating fully-depleted SOI devices. Variation in the uniform thickness of the silicon layer may still be unacceptable and can still impact the threshold voltage of each transistor (memory cell) on the SOI substrate. Accordingly, there is a need for a simple approach to producing highly controlled thicknesses for the silicon layer of SOI substrates for fully-depleted applications.
SUMMARY
Accordingly, various embodiments of the present invention are directed to a process of fabricating a silicon-on-insulator (SOI) substrate. Such a process comprises forming a dielectric layer on a surface of a semiconductor wafer; forming a barrier layer having a hardness substantially greater than the dielectric layer, on the dielectric layer; forming a first trench through a portion of the barrier layer; forming a second trench through the barrier layer and the dielectric layer to expose a portion of the semiconductor wafer; growing a silicon layer from the exposed portion of the semiconductor wafer to fill the second trench and the first trench; and planarizing the silicon layer using the barrier layer as a polish-stop layer to isolate the silicon within the first trench from the silicon in the second trench.
REFERENCES:
patent: 5707486 (1998-01-01), Collins
patent: 5710073 (1998-01-01), Jeng et al.
patent: 5960313 (1999-09-01), Jun
patent: 6077773 (2000-06-01), Lin
Antonelli Terry Stout & Kraus LLP
Everhart Caridad
Intel Corp.
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