Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-10-25

2001-06-26

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S552000, C257S565000

Reexamination Certificate

active

06252269

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a dynamic RAM, and in particular to a semiconductor memory device which has a collector-grounded transistor and which prevents the leakage of an electric charge from a memory cell.
2. Related Arts
A dynamic RAM, which has a number of memory cells, each of which is constituted by a cell transistor and a cell capacitor, is widely employed as a large capacity high-speed memory. For such a memory device, a memory cell area wherein a plurality of memory cells are formed and an area wherein peripheral circuits are formed are provided at the surface of a semiconductor substrate. An MOS cell transistor, which is connected to a bit line and to a word line, and a cell capacitor, which is connected to the cell transistor, are formed in the memory cell area. A CMOS circuit, and a reference voltage generator, which employs a PNP bipolar transistor, are formed in the peripheral circuit formation area.
To provide a CMOS circuit as a peripheral circuit, for example, a P-type well region and an N-type well region are formed in a P-type semiconductor substrate, and an N-type channel MOS transistor and a P-type channel MOS transistor are formed in each well region. In the memory cell area, a back bias voltage, which is lower than the ground voltage, is applied to the channel region, so that a high threshold voltage is set for the cell transistor to reduce current leakage in the OFF state. Therefore, the memory cell area is formed in a P-type well region which is separated from a well region wherein the peripheral circuits are formed, and the back bias voltage is applied to the P-type well region.
FIG. 1
is a cross-sectional view of the structure of a conventional semiconductor memory device. A P-type well region P-WellA and an N-type well region N-WellB are formed in a P-sub semiconductor substrate
10
. Although not shown, an N-type channel MOS transistor and a P-type channel MOS transistor are also formed in each well region. A P-type emitter region
12
and an N-type base contact region
13
are formed close to the P-type well region P-WellA in the N-type well region N-WellB, and a P-type collector contact region
14
is formed in the P-type well region P-WellA, so as to form a lateral PNP transistor. Such a lateral PNP transistor is employed as a reference voltage generator, as will be described later. In this case, the ground voltage is set for the collector contact region
14
, and accordingly, the ground voltage is maintained for the P-type substrate
10
.
A P-type well region P-WellC, which serves as the memory cell area, is formed in the N-type well region N-WellB, and is electrically separated from the P-type substrate
10
. Therefore, in the P-type well region P-WellC a back bias voltage V
BB
is maintained, which is lower than the ground voltage. A drain region
15
and a source region
16
for a cell transistor Tc are formed in the P-type well region P-WellC, and a back bias voltage V
BB
is applied to the P-type well region P-WellC. A cell capacitor Qc is connected to the source region
16
of the cell transistor Tc.
In the conventional structure in
FIG. 1
, the P-type well region P-WellC, wherein a memory cell is provided, is formed in the N-type well region N-WellB using the ion implantation method and the thermal diffusion method. Therefore, the impurity concentration of the P-type well region P-WellC can not be very high. As a result, between the N-type source region
16
and the P-type well region P-WellC an energy barrier at a PN junction can not be set high, and the occurrence of current leakage can not be prevented.
The storage of information in a memory cell is performed whether or not an electric charge is accumulated in the cell capacitor Qc. Therefore, current leakage between the source region
16
and the P-type well region P-WellC results in the loss of stored information during a refresh cycle. In order to prevent the loss of data, the refresh cycle must be shortened.
SUMMARY OF THE INVENTION
It is one objective of the present invention to provide a semiconductor memory device for which a current leakage characteristic of a memory cell is enhanced.
It is another objective of the present invention to provide a new structure for a semiconductor memory, in which a PNP transistor having a grounded collector is provided as a peripheral circuit and for which the current leakage characteristic of the memory cell is improved.
To achieve the above objectives, according to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.
With this structure, unlike the prior art, the P-type first well region, which serves as a memory cell area, is not formed in an N-type well region, so that the first well region having high impurity concentration can be provided and current leakage at a junction in a cell transistor can be reduced. Furthermore, since the deeper, N-type second well region is formed by implanting the high energy N-type impurity, a high temperature annealing process is not required, a semiconductor wafer having a large diameter can be employed, and the manufacturing costs can be reduced. Also, the P-type well region, which constitutes the collector for the PNP transistor, can be separated from the substrate, and for it the ground voltage can be maintained.
To achieve the above objectives, according to another aspect of the present invention, a semiconductor memory device having a memory cell, which includes a cell transistor connected to both a bit line and a word line, and a cell capacitor connected to the cell transistor, and a PNP transistor having at the least a grounded collector, comprises:
a P-type semiconductor substrate;
a P type first well region, which is formed at the surface of the P-type semiconductor substrate;
an N type second well region, which is formed at the surface of the semiconductor substrate and is adjacent to the first well region, and which is deeper than the first well region;
a P type third well region, which is formed in the second well region and connected to a ground voltage; and
a P-type emitter region, which is formed in the second well region and separated from the third well region by a predetermined distance,
wherein the first well region is connected to a back bias voltage level lower than the ground voltage, and the cell transistor is formed in the first well region, and
wherein the P type third well region, the P-type emitter region and the N type second well region constitute the PNP transistor.


REFERENCES:
patent: 5181091 (1993-01-01), Harrington et al.
patent: 5668755 (1997-09-01), Hidaka
patent: 5726475 (1998-03-01), Sawada et al.
patent: 5894145 (1999-04-01), Chen et al.
patent: 6025621 (2000-02-01), Lee et al.

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