Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2000-05-30
2001-09-11
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S189060, C365S230060, C365S149000, C365S154000
Reexamination Certificate
active
06288952
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a system for improved memory cell access, and in particular to a booted column access system for rapid memory cell read and write.
BACKGROUND OF THE INVENTION
Improvements in memory device applications result in larger cell arrays and faster memory access requirements. For example, dynamic random access memories (DRAMs) use an array of memory cells, sense amplifiers, drivers and support electronics to manage data read, data write and cell refresh operations. The memory cells are generally miniature capacitors which vary in stored charge according to the voltage written to the cell. Since each memory cell has leakage losses, each cell must be refreshed periodically to prevent loss of the information in each cell. This is called a “writeback” operation and is performed by periodically reading each cell and refreshing the cell by internally writing a logic one to the cells storing a one. Additionally, each cell is rewritten upon a read instruction, since the reads are destructive without the immediate rewrite.
Static memories (SRAMs) include an array of active memory cells which maintain a programmed logic state without the need for refresh. Increasingly larger memory cell arrays add to the latency of cell read and write operations.
Therefore, there is a need in the art for a system for faster memory cell access and refresh. The system should be implemented with the fewest number of modifications to avoid complications to the chip topology and increased power dissipation.
SUMMARY OF THE INVENTION
The present disclosure describes a memory access system for improved memory cell read and write. The present disclosure describes in detail a limited number of environments in which the present invention may be practiced, however, other applications and environments exist in which the present invention may be practiced.
One environment in which present memory technology may be used is DRAM circuits. In DRAM architectures, a single write driver and I/O sense amplifier are generally shared among a number of columns in a memory array. The sharing is performed by multiplexing the memory array columns using a number of passgates which programmably interconnect a pair of digit lines to the write driver and I/O sense amplifier. Each passgate isolates the digit lines from the write driver and I/O sense amplifier and each is controlled by a column select signal during a read or write operation to a selected memory cell.
In one embodiment of the present memory access system, a voltage booster is used to increase the column select signal voltage applied to the passgate to avoid a voltage drop across the passgate during memory cell read and write operations.
In an alternate embodiment, the voltage booster is limited to only specific memory cell operations. For example, the voltage booster is applied only during a write operation, but not during the read operation.
Other applications and embodiments are described, such as a static memory application, other circuit embodiments, and the use of different boost voltages, however, these examples are for illustrating the present memory access system, and are not intended in an exclusive or limiting sense.
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Ho Hoai V.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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