Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1997-12-18
2001-01-23
Cabeca, John W. (Department: 2752)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S154000, C711S156000
Reexamination Certificate
active
06178483
ABSTRACT:
TECHNICAL FIELD
This invention relates to data processing systems and, more particularly, to a system for prefetching data read by a PCI host from an external memory.
BACKGROUND ART
The growth in computer applications that require heavy data traffic and the increasing availability of high-speed transmission lines create a need for a data switching system able to manage a huge amount of data at high rates. Such a data switching system controlled by a host processor has a large external memory for storing data. A peripheral component interconnect (PCI) bus may be employed to provide intercommunication between the host processor and the memory.
The address and data signals on the PCI bus are time multiplexed on the same 32 pins (AD
0
through AD
31
). On the one clock cycle, the combined address/data lines carry the address values to move information between the PCI host and the memory. On the next cycle, the same lines switch to carrying the actual data.
To reduce latency when the PCI host reads data from the external memory, it would be desirable to provide a system for prefetching information expected to be read by the PCI host from the memory, prior to its actual reading by the host.
DISCLOSURE OF THE INVENTION
Accordingly, an advantage of the present invention is in providing a system for prefetching information expected to be read by a PCI host from an external memory, prior to its actual reading by the host.
The above and other advantages of the invention are achieved, at least in part, by providing a data communication system for supporting data exchange between communication ports that comprises a memory interface for interfacing the system with a memory, and a host interface for interfacing the system with a host. For example, a PCI interface may interface the system with a PCI host. Read prefetch buffers are arranged between the host interface and the memory interface for storing data prefetched from the memory in anticipation of a request from the host to read the data from the memory.
In accordance with one aspect of the invention, the data is automatically prefetched from the memory when a data pointer indicating that the data is queued for transmission to the host is detected at a predetermined communication port. For example, the predetermined communication port may support data transfer to an expansion bus coupled to the host interface for interconnecting multiple data communication switches.
The host interface may compare a read address provided by the host with the address of the prefetched data to transfer the prefetched data from the read prefetch buffer to the host if an address match is detected. If no address match is detected, data having the address provided by the host is prefetched from the memory into the read prefetch buffers.
In accordance with another aspect of the invention, the read prefetch buffers may be arranged in streams connected in parallel between the host interface and the memory interface. The number of streams is preprogrammed in accordance with the number of anticipated host accesses to non-sequential sections of the memory.
In accordance with a further aspect of the invention, write posting buffers are arranged between the host interface and the memory interface for temporarily storing data to be written by the host into the memory.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5515376 (1996-05-01), Murphy et al.
patent: 5564026 (1996-10-01), Amini et al.
patent: 5721839 (1998-02-01), Callison et al.
patent: 5771359 (1998-06-01), Galloway et al.
patent: 5870567 (1999-02-01), Hausauer et al.
patent: 5881253 (1999-03-01), Seeman
Kerstein Denise
Runaldue Thomas J.
Advanced Micro Devices , Inc.
Cabeca John W.
Tzeng Fred F.
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