Method of forming junction leakage free metal silicide in a...

Details Method of forming junction leakage free metal silicide in a... Method of forming junction leakage free metal silicide in a...

1998-11-04

2001-03-20

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S685000

Reexamination Certificate

active

06204177

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor device manufacturing, and more particularly, to the formation of low resistivity self-aligned silicide regions on the gate and source/drain junctions with reduced junction leakage.
BACKGROUND OF THE INVENTION
In the manufacture of integrated circuits, a commonly used practice is to form silicide on source/drain regions and on polysilicon gates. This practice has become increasingly important for very high density devices where the feature size is reduced to a fraction of a micrometer. Silicide provides good ohmic contact, reduces the sheet resistivity of source/drain regions and polysilicon gates, increases the effective contact area, and provides an etch stop.
A common technique employed in the semiconductor manufacturing industry is self-aligned silicide (“salicide”) processing. Salicide processing involves the deposition of a metal that forms intermetallic with silicon (Si), but does not react with silicon oxide or silicon nitride. Common metals employed in salicide processing are titanium (Ti), cobalt (Co), and nickel (Ni). These common metals form low resistivity phases with silicon, such as TiSi
2
, CoSi
2
and NiSi. The metal is deposited with a uniform thickness across the entire semiconductor wafer. This is accomplished using, for example, physical vapor deposition (PVD) from an ultra-pure sputtering target and a commercially available ultra-high vacuum (UHV), multi-chamber, DC magnetron sputtering system. Deposition is performed after both the polysilicon gate and the source/drain junction formation. After deposition, the metal blankets the polysilicon gate electrode, the oxide spacers, the oxide isolation, and the exposed source and drain electrodes. A cross-section of an exemplary semiconductor wafer during one stage of a salicide formation process in accordance with the prior art techniques is depicted in FIG.
1
.
As shown in
FIG. 1
, a silicon substrate
10
has been provided with the source/drain junctions
12
,
14
and a polysilicon gate
16
. Oxide spacers
18
have been formed on the sides of the polysilicon gate
16
. The refractory metal layer
20
, comprising cobalt, for example, has been blanket deposited over the source/drain junctions
12
,
14
, the polysilicon gate
16
and the spacers
18
. The metal layer
20
also blankets oxide isolation regions
22
that isolate the devices from one another.
A first rapid thermal anneal (RTA) step is then performed at a temperature of between about 450°-700° C. for a short period of time in a nitrogen atmosphere. The nitrogen reacts with the metal to form a metal nitride at the surface of the metal, while the metal reacts with silicon and forms silicide in those regions where it comes in direct contact with the silicon. Hence, the reaction of the metal with the silicon forms a silicide
24
on the gate
16
and source/drain regions
12
,
14
, as depicted in FIG.
2
.
After the first rapid thermal anneal step, any metal that is unreacted is stripped away using a wet etch process that is selective to the silicide. A second, higher temperature rapid thermal anneal step, for example above 700° C., is applied to form a lower resistance silicide phase of the metal silicide. The resultant structure is depicted in
FIG. 3
in which the higher resistivity metal silicide
24
has been transformed to the lowest resistivity phase metal silicide
26
. For example, when the metal is cobalt, the higher resistivity phase is CoSi and the lowest resistivity phase is CoSi
2
. When the polysilicon and diffusion patterns are both exposed to the metal, the silicide forms simultaneously over both regions so that this method is described as “salicide” since the suicides formed over the polysilicon and single-crystal silicon are self-aligned to each other.
Titanium is currently the most prevalent metal used for salicide processing in the integrated circuit industry, largely because titanium is already employed in other areas of 0.5 micron CMOS logic technologies. In the first rapid thermal anneal step, the so-called “C49” crystallographic titanium phase is formed, and the lower resistance “C54” phase forms during the second rapid thermal anneal step. However, the titanium silicide sheet resistance rises dramatically due to narrow-line effects. This is described in European Publication No. 0651076. Cobalt silicide (CoSi
2
) has been introduced by several integrated circuit manufacturers as the replacement for titanium silicide. Since cobalt silicide forms by a diffusion reaction, it does not display the narrow-line effects observed with titanium silicide that forms by nucleation-and-growth. Some of the other advantages of cobalt over alternative materials such as platinum or palladium are that cobalt silicide provides low resistivity, allows shallow junctions, and has a reduced tendency for forming diode-like interfaces.
The formation of CoSi
2
is a known two-step process. The higher resistivity phase CoSi forms during a first rapid thermal anneal step (RTA
1
), and the lower resistivity phase CoSi
2
forms during a second rapid thermal anneal step (RTA
2
). During the first reaction to form CoSi, cobalt is the diffusing species when the temperature is less than 500° C. In the second reaction in which CoSi
2
is formed, silicon is the diffusing species. As is well known, a diffusing species will always diffuse along the fastest path. In the cobalt layer deposited on the silicon, there are grain boundaries. Diffusion is faster along a grain boundary in comparison to the bulk of a grain. A schematic enlarged view of the cobalt layer and the silicon layer is depicted in FIG.
4
.
The grain boundaries
25
in the cobalt layer
20
form the fastest path for cobalt to preferentially diffuse along during the first rapid thermal anneal step to form CoSi (reference numeral
24
). As can be seen in
FIG. 4
, the areas underneath the grain boundaries
25
form a locally thicker silicide
24
and a relatively rough interface between the CoSi
24
and the underlying silicon
12
. This roughness can lead to junction leakage, such as that caused by the structure depicted in FIG.
3
. The junction leakage imposes a limitation as the integrated circuit industry progresses toward shallow junctions as a method for improving device switching speed.
SUMMARY OF THE INVENTION
There is a need for a method of producing ultra-shallow junctions and employing salicide technology with reduced junction leakage, allowing shallower junction fabrication and improved device performance.
This and other needs are met by embodiments of the present invention which provide a method of forming metal silicide in a semiconductor wafer with reduced junction leakage, comprising tile steps of introducing an alloy at cobalt grain boundaries within a cobalt layer that overlays a silicon layer, and annealing the cobalt layer and the silicon layer to form metal silicide regions.
By introducing an alloy at the cobalt grain boundaries, by precipitation, for example, cobalt diffusion at the grain boundaries is retarded during a first rapid thermal annealing step. Bulk diffusion is encouraged, and a more uniform silicide film with reduced interface roughness is produced. Since the interface roughness is reduced with the methods of the present invention, junction leakage is reduced. This allows shallower junctions to be fabricated, leading to devices with improved performance.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of producing silicide film in a semiconductor device. The method comprises introducing an alloy at grain boundaries in a refractory metal layer that overlays a silicon layer. The metal layer and the silicon layer are treated to form silicide regions.
The earlier stated needs are met by still further embodiments of the invention, which provide a semiconductor device having silicide regions with reduced interface roughness between the silicide regions and device junctions. The semiconductor device has a refractory metal layer

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