Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1998-06-08

2001-05-29

Lee, Thomas (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000, C713S600000

Reexamination Certificate

active

06240524

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit operating in synchronism with a clock signal.
2. Description of Related Art
Referring to
FIG. 12
, there is shown a block diagram illustrating one example of a prior art semiconductor integrated circuit.
In the prior art, this type of semiconductor integrated circuit was so configured that the whole of the semiconductor integrated circuit is caused to operate in synchronism with one clock signal in order to surely execute an arithmetic and logic operation and transmission of signals. In addition, this type of semiconductor integrated circuit is generally divided into circuit blocks in units of function, and data signals and control signals are transferred between the circuit blocks. Here, for simplification of consideration, it is assumed that the shown semiconductor integrated circuit is composed of three circuit blocks, namely, a circuit block A,
10
, a circuit block B,
20
and a circuit block C,
30
. However, even if the semiconductor integrated circuit is composed of more than three circuit blocks, what will be discussed below will hold similarly. Namely, the same clock signal
1
is supplied to all the circuit blocks. The circuit block A,
10
fetches a data signal
150
supplied from an external device and data signals
110
and
310
supplied from the other blocks, and executes a processing for each clock period to output a data signal
110
to another block. Similarly, for each clock period, each of the circuit block B,
20
and the circuit block C,
30
fetches data, executes a processing and output data to another block. In each of the circuit blocks, the clock signal having the same frequency, generated in one common signal source, is received, an intermediate data is held in a register circuit or a flipflop circuit, which is one constituent included in the circuit block, and then, a signal processing is executed for the intermediate data, and the result of the processing is written into the register circuit or the flipflop circuit in response to a next signal. Although the control signals are not shown in
FIG. 12
, by considering that the control block is one circuit block, the control signals are supplied to the other circuit block in the form similar to that of the data signals. Alternatively, each circuit block can include a control circuit. In this case, the control signal is supplied in parallel to the data signal.
In this circuit construction, it is necessary to reduce a clock skew, namely, to supply the clock signal to the register circuits and the flipflop circuits in all the circuits with the same delay time and to make the changing timing of the clock signals supplied to these circuits consistent to each other. Japanese Patent Application Pre-examination Publication No. JP-A-08-030655, (an English abstract of JP-A-08-030655 is available from the Japanese Patent office and the content of the English abstract of JP-A-08-030655 is also incorporated by reference in its entirety into this application) discloses a designing method for reducing the clock skew.
In addition, S. KOZU et al “A 100 Mkz, 0.4 W RISC Processor with 200 MHz Multiply-Adder, using Pulse-Register Technique”, 1996 IEEE International Solid-State Circuits Conference, Digest of Slide-Supplement, Session FA 8.6, pp 106-107, February, 1996, reports an example in which a deviation is intentionally introduced in the clock signal, so that the clock period is caused to be quasi-elongated only in some circuit, and therefore, a processing time longer than that for the other circuits is allocated. Clock signals are derived from one signal. For example, a circuit operating with a deviated clock signal has a modified number of clock buffers, so that, at a designing stage a delay time from a main stream clock signal is deviated from the other circuit portions.
However, the following problems have been encountered.
A first problem is that it is difficult to distribute the clock signal to the whole of the semiconductor integrated circuit with the same delay time.
The reason for this is as follows: The circuit scale of the semiconductor integrated circuit has an inclination of increasing more and more, and therefore, the number of flipflops requiring the clock signal correspondingly increases, with the result that it has become difficult to design the circuit so as to reduce the skew of the clocks supplied to respective flipflops. In addition, since the size of circuit elements included in the semiconductor integrated circuit becomes small, the influence of variation in the manufacturing process is large, and therefore, even if the distribution delay of the clock signal is equalized at the designing stage, since the delay time is different from one circuit element to another in an actual circuit, the clock skew occurs. Alternatively, in the case that the derived is intentionally deviated in the clock signal, it is necessary to determine the amount of deviation at the designing stage, and there is no other than to control the delay time from the clock signal source to the respective flipflop.
A second problem is that the clock skew greatly lowers the performance of the integrated circuit.
The reason for this is as follows: In order to elevate the performance of the integrated circuit, it is necessary to shorten the clock period so that many processing must be executed for a shortened time. However, if there is a clock skew, the processing cannot be executed for the time of the clock skew in order to avoid error in the signal transfer, and therefore, the clock period must be made long.
A third problem is that the power consumption is large.
The reason for this is as follows. If the clock frequency is made high in order to elevate the performance of the integrated circuit, the power consumption correspondingly becomes large. If the clock frequency is determined for the whole of the integrated circuit, even if a the amount of processing is small, the circuit must be operated at the same clock frequency.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit, which has overcome the above mentioned defects of the conventional one.
Another object of the present invention is to provide a semiconductor integrated circuit capable of ensuring the operation even if the semiconductor integrated circuit becomes large in scale so that the skew of the clock distributed to the whole of the chip becomes large.
Still another object of the present invention is to provide a semiconductor integrated circuit capable of reducing the electric power consumed by the clock signal distributed to the whole of the integrated circuit and the power consumption of the circuits operating with the clock signal.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor integrated circuit operating in synchronism with a clock signal, the whole of the semiconductor integrated circuit being divided into a plurality of circuit blocks in units of a function, the semiconductor integrated circuit being so configured that different clock signals are supplied to the circuit blocks, respectively, each of the circuit blocks being so constructed by taking into consideration the size of clock buffers and the balance in load of the clock buffers in order to minimize the clock skew, and a data signal between two circuit blocks of the circuit blocks being transferred through a queue which is controlled by the clock signal supplied to the two circuit blocks.
The clock signals supplied to the respective circuit blocks can be generated in one common clock signal source, but supplied through respective independent paths. Alternatively, the clock signals supplied to the respective circuit blocks can be generated in different PLL (phase locked loop) circuits, respectively.
In addition, the clock signals supplied to the respective circuit blocks c

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